正交时频空(Orthogonal Time Frequency Space,OTFS)技术在高速移动环境下表现出对时延扩展和多普勒效应的强鲁棒性,显著提升了通信系统在移动场景下的可靠性。针对多用户OTFS系统,提出一种基于非正交多址接入(Non-Orthogonal Multiple ...正交时频空(Orthogonal Time Frequency Space,OTFS)技术在高速移动环境下表现出对时延扩展和多普勒效应的强鲁棒性,显著提升了通信系统在移动场景下的可靠性。针对多用户OTFS系统,提出一种基于非正交多址接入(Non-Orthogonal Multiple Access,NOMA)的信号检测器,该检测器利用共轭梯度法和OTFS正反变换实现OTFS-NOMA系统的信号检测。进一步,针对用户间干扰大和检测器梯度下降收敛慢的问题,提出一种模型驱动神经网络信号检测器。该检测器引入抑制用户间干扰的学习参数,并将执行过程中产生的中间变量嵌入到神经网络中作为学习参数。实验结果表明,相较于现有的信号检测器,所提的模型驱动神经网络信号检测器误比特率性能具有更优表现。展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2~0 3dB or less lost comparing to float simulation.展开更多
摘要正交时频空(Orthogonal Time Frequency Space,OTFS)技术在高速移动环境下表现出对时延扩展和多普勒效应的强鲁棒性,显著提升了通信系统在移动场景下的可靠性。针对多用户OTFS系统,提出一种基于非正交多址接入(Non-Orthogonal Multiple Access,NOMA)的信号检测器,该检测器利用共轭梯度法和OTFS正反变换实现OTFS-NOMA系统的信号检测。进一步,针对用户间干扰大和检测器梯度下降收敛慢的问题,提出一种模型驱动神经网络信号检测器。该检测器引入抑制用户间干扰的学习参数,并将执行过程中产生的中间变量嵌入到神经网络中作为学习参数。实验结果表明,相较于现有的信号检测器,所提的模型驱动神经网络信号检测器误比特率性能具有更优表现。
摘要在自组织映射(Self-organizing Map,SOM)模型的训练过程中,不同类数据对权重矩阵的更新有不同作用,某一类数据对权重矩阵的更新会对其他类获胜神经元特征向量产生偏离其数据特征的影响,从而降低算法聚类精度。针对以上问题,提出一种改进的基于置信度SOM模型(Improved Confidence-based SOM Model,icSOM)。样本数据首先由K-means算法初步分类,为模型训练提供更多的数据信息;然后将预分类后的数据分别训练相互独立的SOM模型,以消除不同类之间的影响;最后在传统SOM模型基础上提出置信度矩阵概念,通过综合判断获胜神经元的置信度及其与输入数据间的欧氏距离最终得到置信神经元,根据置信神经元所属类别给数据分配聚类标签。在鸢尾花数据集(Iris)及葡萄酒数据集(Wine)上利用icSOM进行聚类分析,实验结果表明,所提算法可以更好地处理样本数据,取得了较好的聚类效果。
摘要A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2~0 3dB or less lost comparing to float simulation.