期刊文献+
任意字段
题名或关键词
题名
关键词
摘要
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息
共找到1,986篇文章
< 1 2 … 100 >
每页显示 20 50 100
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
显示方式：
A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA) 认领 引用 被引量：2
1
作者 胡文静 仇润鹤 李外云 《Journal of Donghua University(English Edition)》 EI CAS 2012年第2期193-196,共4页
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ... In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method. 展开更多
关键词 variable digital filter(VDF) field programmable gate array(FPGA) embedded micro-processor(EMP)
暂未订购 下载PDF
一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现 认领 引用 被引量：5
2
作者 曹凤莲 沈庆宏 +1 位作者 盛任农 高敦堂 《南京大学学报（自然科学版）》 CAS 北大核心 2006年第4期362-367,共6页
投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(F... 投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图. 展开更多
关键词 图像处理 梯形校正 Field Programmable Gate Array 锯齿失真
暂未订购 下载PDF
Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA) 认领 引用 被引量：1
3
作者 Johnson A. Asumadu Vaidhyanathan Jagannathan Arkhom Chachavalnanont 《Journal of Intelligent Learning Systems and Applications》 2010年第1期36-42,共7页
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv... An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems. 展开更多
关键词 Multi-Fuzzy Logic Controller (MFLC) Field Programmable Gate Array (FPGA) Buck-Boost Converter Boolean Look-Up Table Co-Integration
暂未订购 下载PDF
A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array 认领 引用 被引量：1
4
作者 陈永军 《Journal of Chongqing University》 2008年第3期228-233,共6页
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr... A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance. 展开更多
关键词 fuzzy control direct torque control field programmable gate array permanent magnet synchronous motor
暂未订购 下载PDF
Implementation of Dynamic Matrix Control on Field Programmable Gate Array 认领 引用 被引量：1
5
作者 兰建 李德伟 +1 位作者 杨楠 席裕庚 《Journal of Shanghai Jiaotong university(Science)》 EI 2011年第4期441-446,共6页
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme... High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. 展开更多
关键词 model predictive control(MPC) dynamic matrix control(DMC) quadratic programming(QP) active set programmable logic device field programmable gate array(FPGA)
暂未订购 下载PDF
Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software 认领 引用
6
作者 LIU Bojiang YAN Ran +2 位作者 CHAI Haiyan HAN Xinyu TANG Longli 《Journal of Donghua University(English Edition)》 CAS 2018年第5期426-429,共4页
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep... In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment. 展开更多
关键词 Field Programmable Gate Array(FPGA) fault prediction diagnosis
暂未订购 下载PDF
Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array 认领 引用
7
作者 李四青 刘华 《Journal of Shanghai Jiaotong university(Science)》 EI 2017年第2期156-160,共5页
A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to ... A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg. 展开更多
关键词 capsule endoscope portable receiver compression algorithm field programmable gate array(FPGA)
暂未订购 下载PDF
MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS 认领 引用
8
作者 Cheng Xiaoyan Yang Haigang +3 位作者 Yin Tao Wu Qisong Zhi Tian Liu Fei 《Journal of Electronics(China)》 2014年第2期129-142,共14页
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr... The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations. 展开更多
关键词 Field Programmable Gate Array(FPGA) Field Programmable Analog Array(FPAA) Sensor Mixed-grained Configurable Analog Block(CAB) Correlated Double Sampling(CDS)
暂未订购 下载PDF
Programmable array antenna based on nematic liquid crystals for the Ka-band 认领 引用
9
作者 WANG Qiang KE Junchen BAI Lin 《Journal of Southeast University(English Edition)》 EI CAS 2025年第1期78-83,共6页
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph... A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication. 展开更多
关键词 array antenna nematic liquid crystals electronically beam scanning field programmable gate array(FPGA)
暂未订购 下载PDF
LightIN:a versatile silicon-integrated photonic field programmable gate array with an intelligent configuration framework for next-generation AI clusters 认领 引用
10
作者 Ying Zhu Yifan Liu +14 位作者 Xinyu Yang Kailai Liu Xin Hua Ming Luo Jia Liu Siyao Chang Jie Yan Shengxiang Zhang Miao Wu Zhicheng Wang Hongguang Zhang Dong Wang Daigao Chen Xi Xiao Shaohua Yu 《Light: Science & Applications》 SCIE EI CAS CSCD 2026年第5期1736-1750,共15页
Artificial Intelligence models pose serious challenges to intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters.Silicon photonic technologies,due to their hi... Artificial Intelligence models pose serious challenges to intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters.Silicon photonic technologies,due to their high speed,low latency,large bandwidth,and complementary metal-oxide-semiconductor compatibility,have been widely implemented for data transmission and actively explored as photonic neural networks in AI clusters.However,current silicon photonic integrated chips lack adaptability for multifunctional use and hardware-software systematic coordination,which is adverse to the development of photo-electronic AI clusters.Here,we develop a reconfigurable silicon photonic chip with 40 programmable unit cells integrating over 160 components,which,to the best of our knowledge,is the first to realize diverse functions for AI clusters with a chip,from computing acceleration and signal processing to network switching and secure encryption.Using a self-developed testing,compilation,and adjustment framework to the chip without in-chip monitoring photodetectors,we have demonstrated(1)4×4 bi-direction unitary and 3×3 uni-direction non-unitary matrix multiplications,achieving a speed of over 1.92 TOPS with 6.22-bit precision and energy efficiency of 1.875 pJ MAC-1,and neural networks for image recognition with a latency of 260 ps;(2)micro-ring modulator wavelength locking in the 5 to 32 Gb s-1 transmission systems;(3)4×4 photonic channel switching with low to-44 dB inter-channel crosstalk;(4)silicon photonic physical unclonable functions.This optoelectronic processing system,incorporating the photonic chip and its software stack,paves the way for both advanced photonic system-on-chip design and the construction of photo-electronic AI clusters. 展开更多
关键词 artificial intelligence models intelligent configuration framework data transmission photonic neural networks photonic technologiesdue silicon integrated photonic field programmable gate array silicon photonic integrated chips intensive computing
暂未订购 下载PDF
Implimentations of SIMD machine using programmable gate array 认领 引用
11
作者 胡铭曾 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2000年第3期10-13,共4页
Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this ... Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation. 展开更多
关键词 Field Programmable Gate Array Single Instruction Multiple Data Dynamically Programmable Data Array
暂未订购 下载PDF
Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array 认领 引用
12
作者 YI Qing-ming XIE Sheng-li 《Semiconductor Photonics and Technology》 2008年第1期32-36,共5页
In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms... In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption. 展开更多
关键词 orthogonal frequency division multiplex timing synchronization field programmable gate array
暂未订购 下载PDF
FPGA-Based Efficient Programmable Polyphase FIR Filter 认领 引用 被引量：4
13
作者 CHEN He XIONG Cheng-huan +1 位作者 ZHONG Shun-an WANG Hua 《Journal of Beijing Institute of Technology》 EI CAS 2005年第1期4-8,共5页
The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically ... The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry,odd/even taps,from 32 taps up to 256 taps.The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of(160 MHz.) 展开更多
关键词 finite impulse response(FIR)filter polyphase field programmable gate array(FPGA)
暂未订购 下载PDF
基于物理引导神经网络的PMSM速度控制算法及其FPGA实现 认领 引用 被引量：1
14
作者 谭会生 李焕斌 《半导体技术》 CAS 北大核心 2026年第4期352-364,共13页
为提高复杂工况下永磁同步电机(PMSM)动态响应性能和控制算法的执行速度,设计了一个基于物理引导的反向传播神经网络比例积分(PG-BPNN-PI)速度控制算法,并采用现场可编程门阵列(FPGA)结合硬件在环仿真方法进行验证。将PMSM物理模型的信... 为提高复杂工况下永磁同步电机(PMSM)动态响应性能和控制算法的执行速度,设计了一个基于物理引导的反向传播神经网络比例积分(PG-BPNN-PI)速度控制算法,并采用现场可编程门阵列(FPGA)结合硬件在环仿真方法进行验证。将PMSM物理模型的信息嵌入BPNN的反向传播过程中构造新的损失函数,使其梯度更新部分符合电机物理规律,以提高收敛速度;通过Simulink对PG-BPNN-PI速度控制算法进行算法级仿真;采用并行和流水线FPGA结构设计技术对该速度控制算法进行优化,并封装为PG-BPNN-PI IP核,进行功能仿真;最后,结合Simulink与FPGA完成硬件在环仿真验证。结果表明,在PG-BPNN-PI控制策略下,控制系统在稳态和动态响应性能等方面均表现优异;在FPGA时钟频率100 MHz下,执行一次迭代仅需0.46μs。 展开更多
关键词 永磁同步电机(PMSM) 速度控制 物理引导神经网络 现场可编程门阵列(FPGA) 转矩脉动
暂未订购 下载PDF
基于FPGA的宽带高频渔用声呐设计优化与实现 认领 引用
15
作者 程婧 王志俊 +1 位作者 张玉涛 李国栋 《声学技术》 CSCD 北大核心 2026年第2期410-415,共6页
针对宽带高频渔用声呐资源消耗量过大、硬件成本较高等问题,文章提出了一种基于现场可编程门阵列接收链路的优化方法。该方法首先对模数转换信号进行脉冲压缩,并对滤波器系数进行了加窗处理,然后将信号进行下混频处理,最后采用简易求模... 针对宽带高频渔用声呐资源消耗量过大、硬件成本较高等问题,文章提出了一种基于现场可编程门阵列接收链路的优化方法。该方法首先对模数转换信号进行脉冲压缩,并对滤波器系数进行了加窗处理,然后将信号进行下混频处理,最后采用简易求模的方式进行包络处理,从而有效减少了资源消耗。仿真结果表明,在不损失性能的前提下,优化后接收链路的信号处理方法相比优化前的块状随机存取存储器资源消耗减少约86%,乘法器资源消耗减少约80%。消声水池试验结果表明,该方法在2 m量程时可以分辨间距3 cm的两个物体。以该研究方法实现的声呐可应用于核电致灾生物预警、浅水域资源探测以及养殖网箱的生物监测等领域,具有重要的应用价值。 展开更多
关键词 现场可编程门阵列(FPGA) 渔用声呐 信号处理 脉冲压缩
暂未订购 下载PDF
基于FPGA的有源配电网高效实时仿真方法 认领 引用
16
作者 孙充勃 原凯 +3 位作者 宋毅 聂铭 万志伟 丁羽頔 《电力系统及其自动化学报》 CSCD 北大核心 2026年第6期38-45,共8页
针对大规模光伏、风机等分布式电源以及储能装置、电力电子设备等的广泛接入,有源配电网实时仿真存在计算复杂度高、速度慢的问题,提出基于现场可编程门阵列的有源配电网高效实时仿真方法。首先消除传统节点分析法计算流程中节点和支路... 针对大规模光伏、风机等分布式电源以及储能装置、电力电子设备等的广泛接入,有源配电网实时仿真存在计算复杂度高、速度慢的问题,提出基于现场可编程门阵列的有源配电网高效实时仿真方法。首先消除传统节点分析法计算流程中节点和支路之间的耦合计算,离线预处理与仿真步长无关的计算量,降低实时仿真复杂度。在此基础上,设计基于现场可编程门阵列的细粒度并行实时仿真架构,提出全局控制模块、历史量更新模块和电气量更新模块等核心模块硬件设计。最后,实现含详细建模光伏发电单元的配电网实时仿真,仿真步长为4μs,通过与PSCAD/EMTDC和传统硬件设计对比,验证了所提仿真方法与硬件设计的正确性与有效性。 展开更多
关键词 有源配电网 现场可编程门阵列 实时仿真 仿真架构 并行计算
暂未订购 下载PDF
基于FPGA的低照度图像增强算法的研究与实现 认领 引用
17
作者 肖剑 李志斌 +2 位作者 杨进 程鸿亮 胡欣 《计算机工程与科学》 CSCD 北大核心 2026年第1期98-107,共10页
针对深度学习等软件方法实现低照度图像增强算法时,计算量大且复杂、实时性差等问题,实现了一种便于部署到FPGA上的基于Retinex模型的改进的低照度图像增强算法。该算法首先将输入的低照度图像进行RGB色彩空间到YCbCr色彩空间的转换,取... 针对深度学习等软件方法实现低照度图像增强算法时,计算量大且复杂、实时性差等问题,实现了一种便于部署到FPGA上的基于Retinex模型的改进的低照度图像增强算法。该算法首先将输入的低照度图像进行RGB色彩空间到YCbCr色彩空间的转换,取空间中的Y分量作为初始照度分量对其进行自适应伽玛校正和双边滤波处理,提高初始照度分量亮度的同时实现对图像的降噪和对细节的增强,接着依据Retinex模型得到增强图像。将增强后的图像再次转换到YCbCr色彩空间,对Y分量进行多尺度细节增强后转换到RGB色彩空间,作为最终的增强结果输出。实验结果表明,将在FPGA上部署所提出的低照度图像增强算法和在MATLAB上进行算法仿真后的输出图像进行比较,两者的相似度指标SSIM接近1,肉眼很难分辨出两者的差别;在时钟频率为200 MHz时,处理一幅分辨率为1280×720的图像仅需约21 ms;将所提出的算法部署在国产某型号的FPGA上时资源占用率较低,功耗为3.357 W,满足低功耗要求,具有较大的实用意义和工程应用价值。 展开更多
关键词 图像增强 FPGA 自适应伽玛校正 双边滤波 多尺度细节增强
暂未订购 下载PDF
基于混合精度策略的LDLT矩阵分解FPGA加速器设计 认领 引用
18
作者 麦超云 柯晓鹏 +3 位作者 钟东洲 洪晓纯 陈潘荣 苏志远 《计算机应用》 CSCD 北大核心 2026年第4期1218-1226,共9页
针对对称正定矩阵分解算法在现场可编程门阵列(FPGA)上实现时常面临资源消耗大、计算精度与效率难以兼顾等问题,提出一种基于混合精度策略的LDLT分解加速结构。该结构在存储层面采用半精度数降低资源消耗,在计算层面使用单精度数保... 针对对称正定矩阵分解算法在现场可编程门阵列(FPGA)上实现时常面临资源消耗大、计算精度与效率难以兼顾等问题,提出一种基于混合精度策略的LDLT分解加速结构。该结构在存储层面采用半精度数降低资源消耗,在计算层面使用单精度数保障计算精度与数值稳定性。此外,构建多处理单元的并行流水结构,并引入双仲裁机制,以优化数据调度与内存访问过程。加速结构则部署于xczu4ev-sfvc784 FPGA平台上,并在4PE、8PE和16PE这3种并行配置下对4~256阶的对称正定矩阵进行实验。结果显示,所提结构的矩阵分解的计算结果相对误差均在10-3以内,与部分对比方法相比,该结构占用的LUTs资源减少了40%以上,而占用的DSP资源降低了70%。可见,该结构在保持计算精度的同时实现了低硬件开销,提升了吞吐量,具备良好的可扩展性和工程适应性。 展开更多
关键词 LDLT分解 混合精度策略 双仲裁机制 并行流水 现场可编程门阵列
暂未订购 下载PDF
基于FPGA的Kerr光孤子频率梳主动控制系统实现 认领 引用
19
作者 刘康琦 李晨虹 +3 位作者 曲明飞 王鹏飞 赵峰 康松柏 《波谱学杂志》 CAS 2026年第1期104-113,共10页
Kerr光孤子频率梳因具备毫米级尺寸、低阈值泵浦光功率等特点,是目前芯片级光频原子钟研究的热点技术之一.Kerr光孤子形成过程中腔内功率骤降,热效应引起的腔频漂移会显著缩短Kerr光孤子频率梳的寿命.目前已有孤子功率控制、Pound-Dreve... Kerr光孤子频率梳因具备毫米级尺寸、低阈值泵浦光功率等特点,是目前芯片级光频原子钟研究的热点技术之一.Kerr光孤子形成过程中腔内功率骤降,热效应引起的腔频漂移会显著缩短Kerr光孤子频率梳的寿命.目前已有孤子功率控制、Pound-Drever-Hall(PDH)锁频技术以及辅助激光模式等多种主动控制方法来长时稳定Kerr光孤子的研究报道,但是应用于这些方案的电子学控制系统研究则鲜有报道.本文开发一种基于现场可编程逻辑门阵列(Field-Programmable Gate Array,FPGA)的Kerr光孤子频率梳的主动控制系统,并通过孤子功率控制和PDH频率控制两种主动控制方法,分别在MgF2和CaF2微腔中实现了Kerr光孤子频率梳长时间稳定.该控制系统也可以用于其他微腔光梳平台(如Si3N4、AlN、SiO2)的Kerr光孤子频率梳产生与稳定. 展开更多
关键词 Kerr光孤子频率梳 主动控制 现场可编程逻辑门阵列
暂未订购 下载PDF
一种应用于视觉导航的轻量级FPGA图像预处理加速器方案 认领 引用
20
作者 薛仁魁 张杰 +2 位作者 李斌 李萌 吴洋 《中国科学院大学学报（中英文）》 CAS CSCD 北大核心 2026年第2期277-287,共11页
针对视觉导航图像前端的加速处理需求,提出一种基于轻量级、低成本FPGA的图像预处理加速器方案。该方案通过高效的流水线设计以及并行处理技术集成直方图均衡化、FAST特征点检测及多源传感器数据时间同步等关键功能,解决了在有限硬件资... 针对视觉导航图像前端的加速处理需求,提出一种基于轻量级、低成本FPGA的图像预处理加速器方案。该方案通过高效的流水线设计以及并行处理技术集成直方图均衡化、FAST特征点检测及多源传感器数据时间同步等关键功能,解决了在有限硬件资源下实现多功能集成、满足实时性要求、平衡成本与性能、多源传感器信息时间同步,以及实现软硬件协同设计等技术难点。该方案基于Xilinx公司Zynq-7000系列轻量级FPGA实现,在实现低成本的同时大大降低了图像处理延迟。当FPGA以160 MHz的频率运行时,对于1280×720的图像可实现150帧/s的处理速度,提供了一种低成本、高性能的视觉导航图像前端加速解决方案。 展开更多
关键词 图像加速器 直方图均衡化 特征点提取 时间同步 视觉导航 现场可编程门阵列(FPGA)
暂未订购 下载PDF
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
上一页 1 2 … 100 下一页 到第 页
在线咨询 使用帮助 返回顶部 意见反馈