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Hardware/software co-verification platform for EOS design 认领 引用 被引量：2
1
作者 Wang Peng Jin Depeng Zeng Lieguang 《High Technology Letters》 EI CAS 2005年第3期294-297,共4页
Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full... Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform. 展开更多
关键词 Hardware/software co-verification EOS
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Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm 认领 引用
2
作者 张宏烈 张国印 姚爱红 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2010年第4期548-551,共4页
This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second met... This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved. 展开更多
关键词 hardware/software partitioning chaos optimization algorithm maximum entropy reconfigurable system
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A hardware/software co-optimization approach for embedded software of MP3 decoder 认领 引用
3
作者 ZHANG Wei LIU Peng ZHAI Zhi-bo 《Journal of Zhejiang University-SCIENCE A》 SCIE EI CAS 2007年第1期42-49,共8页
In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed st... In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture. 展开更多
关键词 Hardware/software co-optimization DSP Embedded software MP3 decoder
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Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System 认领 引用
4
作者 滕建辅 蔡晓 张涛 《Transactions of Tianjin University》 EI CAS 2015年第4期366-370,共5页
In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution proc... In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,. 展开更多
关键词 hardware/software partitioning scheduling algorithm storage capacity communication
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Solving Hardware/Software Partitioning via a Discrete Dynamic Convexized Method 认领 引用 被引量：1
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作者 LIN Geng 《Wuhan University Journal of Natural Sciences》 CAS CSCD 2019年第4期341-348,共8页
Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is... Hardware/software partitioning is an important step in the design of embedded systems. In this paper, the hardware/software partitioning problem is modeled as a constrained binary integer programming problem, which is further converted equivalently to an unconstrained binary integer programming problem by a penalty method. A local search method, HSFM, is developed to obtain a discrete local minimizer of the unconstrained binary integer programming problem. Next, an auxiliary function, which has the same global optimal solutions as the unconstrained binary integer programming problem, is constructed, and its properties are studied. We show that applying HSFM to minimize the auxiliary function can escape from previous local optima by the increase of the parameter value successfully. Finally, a discrete dynamic convexized method is developed to solve the hardware/software partitioning problem. Computational results and comparisons indicate that the proposed algorithm can get high-quality solutions. 展开更多
关键词 hardware software partitioning binary integer programming local search dynamic convexized method
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New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns 认领 引用
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作者 Yassine Manai Joseph Haggège Mohamed Benrejeb 《Journal of Software Engineering and Applications》 2010年第6期525-535,共11页
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design... This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach. 展开更多
关键词 Embedded Systems Design Patterns Smartcell Hardware/Software Partitioning Intellectual Property
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Optimal hardware/software co-synthesis for core-based SoC desi gns 认领 引用 被引量：4
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作者 Zhan Jinyu Xiong Guangze 《Journal of Systems Engineering and Electronics》 2006年第2期402-409,共8页
A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formulation. Given a SoC integrated with a set of functions and a ... A hardware/software co-synthesis method is presented for SoC designs consisting of both hardware IP cores and software components on a graph-theoretic formulation. Given a SoC integrated with a set of functions and a set of performance factors, a core for each function is selected from a set of alternative IP cores and software components, and optimal partitions is found in a way to evenly balance the performance factors and to ultimately reduce the overall cost, size, power consumption and runtime of the core-based SoC. The algorithm formulates IP cores and components into the corresponding mathematical models, presents a graph-theoretic model for finding the optimal partitions of SoC design and transforms SoC hardware/software co-synthesis problem into finding optimal paths in a weighted, directed graph. Overcoming the three main deficiencies of the traditional methods, this method can work automatically, evaluate more performance factors at the same time and meet the particularity of SoC designs. At last, the approach is illustrated that is practical and effective through partitioning a practical system. 展开更多
关键词 SoC co-synthesis partition IP core software component optimal path.
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Software-hardware co-design accelerates materials simulations 认领 引用
8
作者 Xiaozhe Wang Wei Zhang En Ma 《Journal of Semiconductors》 EI CAS CSCD 2026年第7期28-31,共4页
Accurate atomistic and electronic-structure calculations based on density functional theory(DFT)and DFT-based ab initio molecular dynamics(AIMD)calculations underpin much of modern computational chemistry and material... Accurate atomistic and electronic-structure calculations based on density functional theory(DFT)and DFT-based ab initio molecular dynamics(AIMD)calculations underpin much of modern computational chemistry and materials science[1].DFT calculations offer quantitative insights into chemical bonding,charge transport,phase stability,reaction pathways,etc[2]. 展开更多
关键词 chemical bondingcharge software hardware co design density functional theory dft dft based ab initio molecular dynamics ab initio molecular dynamics aimd calculations materials simulations materials science density functional theory
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Application of Plan-Do-Check-Act cycle based on software, hardware, environment, liveware model in preventing infection after endoscopic mucosal resection 认领 引用
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作者 Wen Li Chun Liu Hai-Yan Zhang 《World Journal of Gastrointestinal Surgery》 SCIE 2026年第3期114-121,共8页
BACKGROUND Endoscopic mucosal resection(EMR)is widely used for superficial gastrointestinal tumors but carries a notable risk of surgical site infection(SSI),which impairs recovery and increases morbidity.Existing inf... BACKGROUND Endoscopic mucosal resection(EMR)is widely used for superficial gastrointestinal tumors but carries a notable risk of surgical site infection(SSI),which impairs recovery and increases morbidity.Existing infection control strategies often lack systematic integration of human,environmental,and procedural factors.The software,hardware,environment,liveware(SHEL)model offers a comprehensive framework to identify such multidimensional risks,while the Plan-Do-Check-Act(PDCA)cycle enables continuous quality improvement.We hypothesized that integrating the SHEL model into a PDCA-based nursing management protocol would significantly reduce post-EMR SSI rates and enhance patient outcomes compared to conventional care.AIM To investigate the effect of a SHEL-based PDCA cycle in preventing EMR infection.METHODS This study was conducted in Shanxi Bethune Hospital with 140 EMR patients,randomly assigned to control(routine perioperative nursing)or observation(SHEL model-integrated PDCA cycle nursing)groups(n=70 each).Outcomes included postoperative incisional infection rate,recovery,operating room care quality,and patient satisfaction.Data were analyzed using χ2 tests and t-tests.RESULTS The incidence of postoperative SSI in the observation group was significantly lower than that in the control group(5.71%vs 18.57%,P=0.020).Postoperative recovery indicators,including first flatus time(7.34±1.37 hours vs 9.89±1.37 hours,P<0.001),first defecation time(12.59±2.42 hours vs 17.21±2.44 hours,P<0.001),first ambulation time(10.01±1.27 hours vs 12.81±1.51 hours,P<0.001),and hospital stay(7.10±1.66 days vs 12.98±1.80 days,P<0.001),were all significantly shorter in the observation group.Operating room care quality scores and overall patient satisfaction(84.29%vs 65.71%,P=0.011)were also significantly higher in the intervention group.CONCLUSION The SHEL-based PDCA cycle significantly reduces infection rates,accelerates recovery,and improves nursing quality and patient satisfaction after EMR. 展开更多
关键词 Postoperative infection Endoscopic mucosal resection Plan-Do-Check-Act cycle Software,hardware,environment,liveware model Surgical site infection
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An efficient GPU-based parallel tabu search algorithm for hardware/software co-design 认领 引用 被引量：9
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作者 Neng Hou Fazhi He +1 位作者 Yi Zhou Yilin Chen 《Frontiers of Computer Science》 SCIE EI CSCD 2020年第5期135-152,共18页
Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel... Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel tabu search algorithm(GPTS)for HW/SW partitioning.A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically.A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS.To further minimize the transfer overhead of GPTS between CPU and GPU,an optimized transfer strategy for GPU-based tabu evaluation is proposed,which considers that all the candidates do not satisfy the given constraint.Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning.The proposed parallelization is significant when considering the ordinary GPU platform. 展开更多
关键词 hardware/software co-design hardware/software partitioning graphics processing unit GPU-based parallel tabu search single kernel implementation kernel fusion strategy optimized transfer strategy
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A Novel Hardware/Software Partitioning Method Based on Position Disturbed Particle Swarm Optimization with Invasive Weed Optimization 认领 引用 被引量：10
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作者 Xiao-Hu Yan Fa-Zhi He Yi-Lin Chen 《Journal of Computer Science & Technology》 SCIE EI CSCD 2017年第2期340-355,共16页
With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on pos... With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on position disturbed particle swarm optimization with invasive weed optimization （PDPSO-IWO） is presented in this paper. It is found by biologists that the ground squirrels produce alarm calls which warn their peers to move away when there is potential predatory threat. Here, we present PDPSO algorithm, in each iteration of which the squirrel behavior of escaping from the global worst particle can be simulated to increase population diversity and avoid local optimum. We also present new initialization and reproduction strategies to improve IWO algorithm for searching a better position, with which the global best position can be updated. Then the search accuracy and the solution quality can be enhanced. PDPSO and improved IWO are synthesized into one single PDPSO-IWO algorithm, which can keep both searching diversification and searching intensification. Furthermore, a hybrid NodeRank （HNodeRank） algorithm is proposed to initialize the population of PDPSO-IWO, and the solution quality can be enhanced further. Since the HW/SW communication cost computing is the most time-consuming process for HW/SW partitioning algorithm, we adopt the GPU parallel technique to accelerate the computing. In this way, the runtime of PDPSO-IWO for large-scale HW/SW partitioning problem can be reduced efficiently. Finally, multiple experiments on benchmarks from state-of-the-art publications and large-scale HW/SW partitioning demonstrate that the proposed algorithm can achieve higher performance than other algorithms. 展开更多
关键词 hardware/software partitioning particle swarm optimization invasive weed optimization communicationcost parallel computing
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OPFEM:architectural design and implementation of a CAE software for finite element modeling and simulation 认领 引用
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作者 Wei Huang Qun Huang +3 位作者 Jie Yang Xiaowei Bai Tianyun He Heng Hu 《Acta Mechanica Sinica》 SCIE EI CAS CSCD 2026年第2期264-333,共70页
To address challenges in architectural extensibility and cross-module collaboration of CAE software,this study proposes OPFEM(open-source Python-based finite element modeling)—an open-source framework featuring a uni... To address challenges in architectural extensibility and cross-module collaboration of CAE software,this study proposes OPFEM(open-source Python-based finite element modeling)—an open-source framework featuring a unified four-layer architecture.The geometric modeling framework achieves plug-in support for geometric kernels through an interface abstraction layer and adapter patterns,decoupling kernel-specific implementations while enabling state machine-driven interaction design and parametric sketching.The pre-processing modules establish multi-level associations among materials,sections,and geometric entities using Composite and Factory patterns,while implementing Observer pattern to ensure geometric-mesh consistency and employing finite-state machines to optimize boundary workflows.The computational modules implement a modular finite element library that decouples topology from element attributes,along with a surface boundary element technique for load conversion and task-scheduling management,validated through a cantilever beam large-deformation case.The post-processing module facilitates standardized data storage and dynamic field visualization through architecture-level standardized interface definitions and hierarchical component design.Collectively,OPFEM achieves full-process integration from parametric modeling to nonlinear solving and visualization,enhancing configuration efficiency and providing an extensible,pattern-driven solution for complex CAE challenges. 展开更多
关键词 Finite element method CAE software architecture Object-oriented programming Modular design Opensource software
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Software and layout optimization of HIRFL-CSR external-target experiment 认领 引用
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作者 Jian-Wang Hong Chen-Lu Hu +29 位作者 Yu-Hong Yu Nu Xu Zhi-Yu Sun Hao Qiu Zhi-Gang Xiao Ming Shao Li-Min Duan Xiong-Hong He Zhi-Hui Xu Yi Wang Dong Han Zi-Xuan Chen Feng-Yi Zhao He-Run Yang Xiang-Lun Wei Rong-Jiang Hu Feng Liu Hua Pei Ya-Ping Wang Ye Tian Zhi Qin Dong-Dong Hu Guo-Dong Shen Li-Jun Mao Wei Wu Wei You Yu-Quan Chen Peng Yang De-Qing Fang Ya-Peng Zhang 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2026年第5期289-297,共9页
Heavy-ion collisions(HICs)is a unique experimental tool for investigating the properties of nuclear matter under extreme conditions in the laboratory.At HIRFL-CSR energies,HICs can create nuclear matter with 2-3 times... Heavy-ion collisions(HICs)is a unique experimental tool for investigating the properties of nuclear matter under extreme conditions in the laboratory.At HIRFL-CSR energies,HICs can create nuclear matter with 2-3 times the saturation density(ρ0).The HIRFL-CSR external-target experiment(CEE)is a large-acceptance spectrometer designed to explore frontier topics in high-energy nuclear physics,such as the QCD phase structure and nuclear matter equation of states.In this letter,we introduce simulation and analysis software for the CEE experiment(CeeROOT).Based on the CEE conceptual design and CeeROOT software,the configurations of its subdetectors were optimized by considering foreseeable physical constraints.The final detector layout of the CEE spectrometer and its acceptances were validated through simulations of U+U collisions at 500 MeV/u and pp collisions at 2.8 GeV,which demonstrated that the CEE experiment will serve as a detector with wide acceptance and multi-particle identification capabilities for studying high-energy nuclear physics topics at HIRFL-CSR energies with pp,pA,and A A collisions. 展开更多
关键词 CEE experiment Simulation software Optimization HIRFL-CSR
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Neurodynamic Optimization Approaches With Fixed-Time Convergence for Nash Equilibrium Seeking:Theory and Hardware Experiment 认领 引用
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作者 Xingxing Ju Xinsong Yang +2 位作者 Chuandong Li Gang Feng Daniel W.C.Ho 《IEEE/CAA Journal of Automatica Sinica》 SCIE EI CSCD 2026年第3期704-714,共11页
The convergence rate is one of the key performance measures for Nash equilibrium(NE)seeking strategies.In this work,we present several novel fast decoupled/coupled time-varying neurodynamic optimization approaches wit... The convergence rate is one of the key performance measures for Nash equilibrium(NE)seeking strategies.In this work,we present several novel fast decoupled/coupled time-varying neurodynamic optimization approaches with fixed-time(FT)convergence to Nash equilibrium seeking in non-cooperative games.The dynamics trajectories are demonstrated to converge to the NE solution within a fixed time from any initial states.The proposed neurodynamic networks exhibit a faster convergence rate with appropriately selected time-varying coefficients.Additionally,the upper bounds of the convergence time of the proposed NE seeking networks are smaller than those for strategies with constant coefficients.The robustness of the proposed NE seeking neurodynamic approaches under bounded perturbations is further studied.The efficacy and practicality of the proposed NE seeking approaches are validated through simulations and field-programmable gate array(FPGA)experiments on duopoly market games. 展开更多
关键词 Fixed-time(FT)convergence hardware implementation Nash equilibrium(NE) neurodynamic optimization approaches
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Towards secure computation and trusted silicon:emerging trends in ISSCC 2026 hardware security 认领 引用
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作者 Wenping Zhu Hanning Wang +1 位作者 Bohan Yang Leibo Liu 《Journal of Semiconductors》 EI CAS CSCD 2026年第7期1-6,共6页
As the semiconductor industry transitions into an era shaped by ubiquitous artificial intelligence,heterogeneous integration,and the prospective impact of cryptanalytically capable quantum computers,hardware security ... As the semiconductor industry transitions into an era shaped by ubiquitous artificial intelligence,heterogeneous integration,and the prospective impact of cryptanalytically capable quantum computers,hardware security is increasingly extending beyond its traditional role as isolated cryptographic engines or standalone blocks[1,2]. 展开更多
关键词 hardware security trusted silicon ubiquitous artificial intelligence artificial intelligenceheterogeneous integrationand semiconductor industry standalone blocks cryptographic engines ISSCC
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Monolithically integrated dual distributed Bragg grating laser with a large hardware key space 认领 引用
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作者 JUNLI WANG LONGSHENG WANG +5 位作者 ZHIWEI JIA YUANYUAN GUO PENGFA CHANG YUNCAI WANG YUWEN QIN ANBANG WANG 《Photonics Research》 SCIE EI CAS CSCD 2026年第5期1866-1873,共8页
Synchronization of chaos in laser diodes has inspired advancements in physical-layer encryption communication,offering benefits such as high speed,extended range,and favorable compatibility.Nonetheless,a significant c... Synchronization of chaos in laser diodes has inspired advancements in physical-layer encryption communication,offering benefits such as high speed,extended range,and favorable compatibility.Nonetheless,a significant challenge persists in developing a synchronous chaotic transceiver with an extensive hardware key space without increasing system complexity.In this study,we propose the utilization of monolithically integrated dual distributed Bragg grating lasers(DDBGLs)to construct a synchronous chaotic transceiver with a large hardware key space. 展开更多
关键词 synchronous chaotic transce laser diodes dual distributed bragg grating lasers synchronization chaos large hardware key space synchronous chaotic transceiver monolithically integrated
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QIMIG:A Quantum-Inspired Evolutionary Framework for Software Library Migration 认领 引用
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作者 Yun Liu Jinghua Zhao +3 位作者 Liang Ma Zijie Huang Lizhi Cai Jianxin Ge 《Computers, Materials & Continua》 SCIE EI 2026年第9期795-812,共18页
Automated library migration reduces refactoring costs but challenges traditional evolutionary algorithms,which often suffer from premature convergence and poor recall in sparse,complex API mapping spaces.To address th... Automated library migration reduces refactoring costs but challenges traditional evolutionary algorithms,which often suffer from premature convergence and poor recall in sparse,complex API mapping spaces.To address this,we propose QIMIG,a multi-objective optimization framework integrating quantum-inspired encoding with quality-aware and greedy heuristic filtering.QIMIG utilizes a probabilistic Q-bit representation to maintain population diversity and avoid local optima.Simultaneously,its heuristic components leverage historical usage context to filter semantic noise and guide the search toward valid mappings.Evaluated on 9 real-world migration rules derived from 57,447 open-source projects,QIMIG statistically significantly outperforms state-of-the-art baselines such as UNSGA-III.The framework achieves a global mean F1-score of 0.92,exceeding the best-performing baseline by an absolute margin of 0.05,and demonstrates strong stability in resolving complex mapping structures. 展开更多
关键词 Library migration API mapping search-based software engineering quantum-inspired evolutionary algorithm multi-objective optimization
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Methods,Algorithms,Codes,and Software for Theoretical and Computational Chemistry 认领 引用
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作者 Bin Jiang 《Chinese Journal of Chemical Physics》 SCIE EI CAS CSCD 2026年第3期301-302,共2页
Theoretical and computational chemistry has profoundly impacted a wide range of disciplines,from chemistry and physics to biology and materials science.In recent years,remarkable advances in electronic structure theor... Theoretical and computational chemistry has profoundly impacted a wide range of disciplines,from chemistry and physics to biology and materials science.In recent years,remarkable advances in electronic structure theory,molecular dynamics,and machine learning methods——coupled with increasingly powerful algorithms and software—have equipped chemists with an unprecedented arsenal of tools to tackle complex chemical problems. 展开更多
关键词 theoretical computational chemistry electronic structure theorymolecular dynamicsand algorithms codes software methods materials sciencein theoretical chemistry
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New Model and Algorithm for Hardware/Software Partitioning 认领 引用 被引量：5
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作者 武继刚 Thambipillai Srikanthan 邹广伟 《Journal of Computer Science & Technology》 SCIE EI 2008年第4期644-651,共8页
This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of har... This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature. 展开更多
关键词 algorithm hardware/software partitioning dynamic programming complexity
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Predicting Software Security Bugs Using Machine Learning and Quality Metrics: An Empirical Study 认领 引用
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作者 Mohamed Diouf Elisée Toe +2 位作者 Manel Grichi Haïfa Nakouri Fehmi Jaafar 《Computers, Materials & Continua》 SCIE EI 2026年第6期436-477,共42页
Software security bugs present significant security risks to modern systems,leading to unauthorized access,data breaches,and severe operational and financial consequences.Early prediction of such vulnerabilities is th... Software security bugs present significant security risks to modern systems,leading to unauthorized access,data breaches,and severe operational and financial consequences.Early prediction of such vulnerabilities is therefore essential for strengthening software reliability and reducing remediation costs.This study investigates the extent to which static software quality metrics can identify vulnerable code and evaluates the effectiveness of machine learning models for large-scale security-bug prediction.We analyze a dataset of 338,442 source files,including 33,294 buggy files,collected from seven major open-source ecosystems.These ecosystems include GitHub Security Advisories(GHSA),Python Package Index(PyPI),OSS-Fuzz(Google’s open-source fuzzing service),Node Package Manager(npm),Packagist(the PHP package repository),Apache Maven,and NuGet(the.NET package manager).Using the Open Source Vulnerabilities(OSV)platform,we identify 7685 confirmed security bugs and extract 25 static software quality metrics per file with the Understand analysis tool.We apply five complementary feature-importance techniques and evaluate eleven machine-learning classifiers under a time-series cross-validation protocol.Our analysis reveals three key findings.First,six core metrics consistently show strong associations with the presence of security bugs across all feature-selection methods.Second,buggy files exhibit substantially higher metric values,with medians approximately three times those of non-buggy files,a pattern we term the“3×rule”;Mann-Whitney U tests confirm that these differences are statistically significant.Third,the machine-learning models achieve strong predictive performance,with XGBoost providing the best results(recall=0.82,precision=0.95,Receiver Operating Characteristic-Area Under the Curve(ROC-AUC)=0.91).Based on these findings,we propose data-driven warning and critical thresholds for the most influential metrics to support proactive security assessment.Overall,this work provides large-scale empirical evidence that software quality metrics,combined with machine learning,offer actionable signals for detecting security bugs and for integrating automated vulnerability prediction into software development workflows. 展开更多
关键词 Security bugs vulnerability prediction software metrics machine learning code complexity software quality
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