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Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication 认领 引用 被引量：4
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作者 WANG Yongqing LIU Donglei +1 位作者 SUN Lida WU Siliang 《China Communications》 SCIE CSCD 2014年第12期94-104,共11页
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)... In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction. 展开更多
关键词 quasi—cyclic code LDPC decoder m in-sum algorithm partial parallel structure lookup table
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Construction of Short-Block Nonbinary LDPC Codes Based on Cyclic Codes 认领 引用 被引量：3
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作者 Hengzhou Xu Baoming Bai +2 位作者 Min Zhu Bo Zhang Yulong Zhang 《China Communications》 SCIE CSCD 2017年第8期1-9,共9页
In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDP... In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that the parity-check matrix H of the resulting code is square and not of full rank, and its row weight and column weight are the same. By replacing the ones in the same column of H with a nonzero element of fi nite fi elds GF(q), a class of NB-LDPC codes over GF(q) is obtained. Numerical results show that the constructed codes perform well over the AWGN channel and have fast decoding convergence. Therefore, the proposed NB-LDPC codes provide a promising coding scheme for low-latency and high-reliability communications. 展开更多
关键词 nonbinary LDPC codes tanner graph isomorphism iterative decoding
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Modified Benes network architecture for WiMAX LDPC decoder 认领 引用 被引量：1
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作者 徐勐 吴建辉 张萌 《Journal of Southeast University(English Edition)》 EI CAS 2011年第2期140-143,共4页
A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not ... A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%. 展开更多
关键词 worldwide interoperability for microwave access（WiMAX） quasi-cycle low density parity check （QC-LDPC） LDPC decoder Benes network
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HARLD:A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding 认领 引用
4
作者 Bing Wang Zi-Rui Ma +6 位作者 Hai-Bin Wu Fu-Lin Zhang Yue Wang Zhi-Hua Fan Wen-Ming Li Xiao-Chun Ye Dong-Rui Fan 《Journal of Computer Science & Technology》 SCIE EI CSCD 2026年第2期774-790,共17页
Low-density parity check(LDPC)decoding is an efficient error correction method in communication systems,especially in 5G networks,which require high performance and low latency;while common general-purpose architectur... Low-density parity check(LDPC)decoding is an efficient error correction method in communication systems,especially in 5G networks,which require high performance and low latency;while common general-purpose architectures cannot meet the requirements.There has been some research on accelerating LDPC decoding,but the current methods still suffer from limitations in performance,flexibility,and communication cost.In this paper,we propose HARLD(Heterogeneous Architecture of RISC-V for LDPC Decoding),a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding,consisting of a CPU and a processing array.Compared with a loosely coupled System-on-Chip(SoC)-bus baseline,the tightly coupled design improves throughput by up to 32.4%and reduces average latency by up to 24.7%across evaluated configurations,while also enhancing resource and energy efficiency:processing element utilization up to 93.5%,instruction RAM utilization increased by up to 4.8x,and energy efficiency improved by up to 24.8%.At the system level,area and power are reduced by 17.6%and 10.2%,respectively,versus the loosely coupled design. 展开更多
关键词 tightly coupled heterogeneous computing architecture low-density parity check(LDPC)decoding RISC-V extension
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Design of a(480,240)CMOS Analog Low-Density Parity-Check Decoder 认领 引用
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作者 Hao Zheng Zhe Zhao +1 位作者 Xiangming Li Hangcheng Han 《China Communications》 SCIE CSCD 2017年第8期41-53,共13页
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons... Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works. 展开更多
关键词 LDPC analog decoder handcraft design reduction probability stopping criterion for analog decoding reusable building block
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Efficient Helicopter-Satellite Communication Scheme Based on Check-Hybrid LDPC Coding 认领 引用 被引量：15
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作者 Ping Wang Liuguo Yin Jianhua Lu 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2018年第3期323-332,共10页
When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the ... When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes. 展开更多
关键词 helicopter-satellite communications check-hybrid Low-Density Parity-Check（LDPC） codes Extrinsic Information Transfer（EXIT） iterative decoding
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Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN 认领 引用
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作者 Sun Shulong Liu Lei Lin Min 《The Journal of China Universities of Posts and Telecommunications》 EI CSCD 2018年第3期65-70,共6页
Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are requi... Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications. 展开更多
关键词 extended min-sum algorithm non-binary LDPC decoder shared comparator architecture
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