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A RISC-V 32-bit microprocessor on two-dimensional semiconductor platform 认领 引用
1
作者 Di Zhang Yang Li 《Journal of Semiconductors》 EI CAS CSCD 2025年第8期2-4,共3页
With the rapid development of information technology,the demand for high-performance and low-power microprocessors continues to grow.Traditional silicon-based semiconductor technologies have encountered numerous bottl... With the rapid development of information technology,the demand for high-performance and low-power microprocessors continues to grow.Traditional silicon-based semiconductor technologies have encountered numerous bottlenecks in performance enhancement,such as drain-induced barrier lowering,reduced mobility caused by interface scattering,and limited current on/off ratios. 展开更多
关键词 two dimensional semiconductor low power risc v microprocessor performance information technology reduced mobility drain induced barrier lowering
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Investigation on microprocessor based waveform control of short circuit transfer CO_2 welding 认领 引用 被引量：1
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作者 朱锦洪 石红信 +2 位作者 李兴霞 刘兆魁 涂益民 《China Welding》 EI CAS 2006年第4期26-29,共4页
A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of co... A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of constant current （CC） power supply could be changed according to transient physical state, and the variable down slope rate control could be used to ensure a stable welding process. The welding experiment results proved the effectiveness of this control approach. 展开更多
关键词 CO2 welding waveform control microprocessor short circuit transfer
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MICROPROCESSOR BASED MODEL FOLLOWING ADAPTIVE CONTROL SYSTEM FOR CSIM DRIVES 认领 引用
3
作者 张春明 左敦稳 王珉 《Transactions of Nanjing University of Aeronautics and Astronautics》 1996年第2期40+35-39,共40页
A model following adaptive control system for CSIM is presented in this paper. A dynamic mathematical model of slip control based system is obtained. With the help of model reducing technique, full order model is redu... A model following adaptive control system for CSIM is presented in this paper. A dynamic mathematical model of slip control based system is obtained. With the help of model reducing technique, full order model is reduced to simplify the design without degrading much of the performance. Model following adaptive control laws in discrete form are derived. These laws satisfy the hyperstability condition for taking care of the load and machine parameter changes of the drive. A microprocessor 8098 is used to develop the speed controller. The implementation of the control system uses only available variables of the reference model and the controlled plant. Experimental results are given to demonstrate the good performance of the system. 展开更多
关键词 induction motors frequency converters microprocessors adaptive control model following
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On-line Cache Resizing for Low-Power Microprocessors 认领 引用
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作者 陈黎明 邹雪城 +1 位作者 雷鑑铭 刘政林 《Journal of Southwest Jiaotong University(English Edition)》 2009年第2期113-122,共10页
We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss sta... We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss. 展开更多
关键词 Low power Cache Cache resizing Microprocessor
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The MMU Implementation of Unity-1 Microprocessor 认领 引用 被引量：2
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作者 宋传华 Cheng +2 位作者 Xu Zhu Dexin 《High Technology Letters》 EI CAS 2003年第4期27-32,共6页
Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management me... Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity 11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform. 展开更多
关键词 Unity 1 MMU TLB table walking microprocessor
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The Automated System of Unified Templates as an Element of Trainability of Microprocessor Relay Protection Devices 认领 引用 被引量：1
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作者 Viktor Nikolaevich Sizykh Aleksey Vasilyevich Daneev +1 位作者 Maksim Viktorovich Vostrikov Konstantin Vladimirovich Menaker 《Journal of Applied Mathematics and Physics》 2021年第12期3045-3057,共13页
The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an a... The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an additional automated system of unified templates necessary for the occurrence of “trainability” elements. The templates will be formed via a separate dedicated channel for transmission, processing and storage of the necessary information, not related to the operation of the terminal, with its subsequent visualization at the workplace of the duty personnel of traction substations, together with information from the “GID” software received via another dedicated wired channel. With the help of such a base of unified preset templates, in the future, it will be possible not only to identify the specific causes of each emergency shutdown but also to reduce their number by dynamically adjusting the existing presets of the standard operation algorithm. 展开更多
关键词 Automated System Microprocessor Relay Protection Devices Feeder Traction Substation
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MICROPROCESSOR BASED PHASELOCKED LOOP SPEED CONTROL SYSTEM FOR AC MOTOR 认领 引用
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作者 金建秋 徐银泉 《Journal of China Textile University(English Edition)》 1991年第3期41-48,共8页
In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is c... In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance. 展开更多
关键词 phase-locked techniques microprocessor control speed control systems
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Security Vulnerabilities in Microprocessors 认领 引用
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作者 Benjamin Ashby Smith Kevin Curran 《Semiconductor Science and Information Devices》 CAS 2021年第1期24-32,共9页
Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can ... Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can leak sensitive user data and information.This report will investigate microarchitecture vulnerabilities focusing on the Spectre and Meltdown exploits and will look at what they do,how they do it and,the real-world impact these vulnerabilities can cause.Additionally,there will be an introduction to the basic concepts of how several PC components operate to support this. 展开更多
关键词 Microprocessors Cybersecurity Microarchitecture security
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Comprehensive Automation of Microprocessor Protection Relay Terminals Operated on AC Railways 认领 引用
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作者 Vostrikov Maksim Viktorovich Daneev Aleksey Vasilyevich +1 位作者 Menaker Konstantin Vladimirovich Sizykh Viktor Nikolaevich 《Journal of Applied Mathematics and Physics》 2022年第2期491-503,共13页
The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. R... The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. Real statistics on the number of microprocessor relay protection operations at the Buryatskaya traction substation are presented, simulation of the real train situation (in accordance with the regime maps of the throughput capacity of the sections of the Trans-Baikal railway) was carried out in the specialized software complex “KORTES”. Based on the results of the analysis of simulation modeling, the process of forming a unified template of settings using neural network technologies is considered, which characterizes only this specific regular train situation. To protect objects in the event of pre-emergency and emergency modes of operation of the traction power supply system, a variant of changing the standard operation algorithm of the TsZA-27.5-FKS (FTS) terminal by introducing additional blocks for calculating the predictive functions of current and voltage has been proposed. 展开更多
关键词 Automated System Microprocessor Relay Protection Devices Feeder Traction Substation
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A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator 认领 引用
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作者 Itaru Hida Shinya Takamaeda-Yamazaki +2 位作者 Masayuki Ikebe Masato Motomura Tetsuya Asai 《Circuits and Systems》 2017年第5期134-147,共14页
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by usin... In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor. 展开更多
关键词 Embedded Microprocessor Reconfigurable Low-Power Accelerator Digital Circuit Architecture
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Digital Filter for Electrocardiogram Preprocessing Based on Microprocessor 认领 引用
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作者 WU Xian-wen WANG Feng 《Chinese Journal of Biomedical Engineering(English Edition)》 CAS 2010年第1期30-34,共5页
This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filte... This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filter to remove these two normal noise signals. Signal from the MIT-BIH electrocardiogram database was used to test the performance of the filter. From the test results, the performance of the digital filer is reDT good. The filter coefficient is an integer number, therefore, the filtering algorithm can be successfully implemented on the microprocessor. 展开更多
关键词 digital filter electrocardiogram microprocessor noise removing MIT-BIH database
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SF VECTOR CONTROL SYSTEM WITH TWO SINGLE CHIP MICROPROCESSORS 认领 引用
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作者 XU Yinquan Cui Gejin 《Journal of China Textile University(English Edition)》 1990年第2期73-78,共6页
This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed... This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper. 展开更多
关键词 vector control single chip microprocessor SPWM waves
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UV Wavelength Tunable Output System Controlled by Microprocessor 认领 引用
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作者 JIANG Wanlu ZHANG Shuqing +1 位作者 WU Zhaoxia WANG Yutian 《Semiconductor Photonics and Technology》 1998年第2期98-103,共6页
UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and t... UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and temperature correct are realized,The wavelength tuned output efficiency in the experiment is better than 97 %. 展开更多
关键词 Method of Difference Microprocessor Control PID Regulation Wavelength Auto-tracking
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Experimental research on transient radiation effects in microprocessors based on SPARC-V8 architecture 认领 引用 被引量：4
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作者 赵元富 郑宏超 +3 位作者 范隆 岳素格 陈茂鑫 杜守刚 《Journal of Semiconductors》 EI CAS CSCD 2015年第11期58-62,共5页
An experimental system is developed for the transient radiation effects testing of an anti-radiation hardened processor. Based on this system, the transient radiation effects in a microprocessor based on SPARC-V8 arch... An experimental system is developed for the transient radiation effects testing of an anti-radiation hardened processor. Based on this system, the transient radiation effects in a microprocessor based on SPARC-V8 architecture was investigated. The dose-rate-soft-error index parameters of the processor were determined according to the test results, as were the influences on the function and timing parameters of the processor. The power supply balance is affected, which caused the system to reset and be the main source of soft errors. The results showed the circuit recovery time is primarily determined by the internal PLL, while the core power and the output-low-IO ports are more sensitive to the transient dose rate effect. The power-integrity-hardened design is proposed to mitigate the transient radiation effect. 展开更多
关键词 microprocessor transient dose rate effect transient radiation effect
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High Performance General-Purpose Microprocessors: Past and Future 认领 引用 被引量：5
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作者 胡伟武 侯锐 +1 位作者 肖俊华 章隆宾 《Journal of Computer Science & Technology》 SCIE EI 2006年第5期631-640,共10页
It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to sim... It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced. 展开更多
关键词 high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor
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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor 认领 引用 被引量：1
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作者 王达 胡瑜 +1 位作者 李华伟 李晓维 《Journal of Computer Science & Technology》 SCIE EI 2008年第6期1037-1046,共10页
This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression struct... This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost. 展开更多
关键词 microprocessor design-for-testability test generation built-in self-test at-speed testing
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开放指令集架构驱动的微处理器结构与设计教学改革 认领 引用
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作者 孙彩霞 王俊辉 +3 位作者 郑重 雷国庆 隋兵才 王永文 《计算机教育》 2026年第4期28-33,共6页
针对微处理器结构与设计课程教学过程中存在的问题,结合开放指令集架构带来的机遇和挑战,从“如何做到理论知识的聚焦凝练、如何做到课程实验的学以致用、如何做到各类学生的因材施教”着手,提出课程教学改革方案,介绍2022—2024学年的... 针对微处理器结构与设计课程教学过程中存在的问题,结合开放指令集架构带来的机遇和挑战,从“如何做到理论知识的聚焦凝练、如何做到课程实验的学以致用、如何做到各类学生的因材施教”着手,提出课程教学改革方案,介绍2022—2024学年的改革实践,最后说明改革成效,旨在为全国高校微处理器设计领域人才培养提供参考。 展开更多
关键词 开放指令集架构 微处理器结构与设计 教学改革
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人工智能时代微处理器设计课程教学改革 认领 引用
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作者 王素玉 王伟东 何坚 《计算机教育》 2026年第6期52-56,共5页
在人工智能技术高速发展、算力需求持续升级的时代背景下,微处理器作为算力核心,其自主设计能力已成为关键技术支撑,对高校人才培养提出更高要求。首先分析当前微处理器设计课程在教学内容、育人模式、实践环节等方面的现状与痛点,针对... 在人工智能技术高速发展、算力需求持续升级的时代背景下,微处理器作为算力核心,其自主设计能力已成为关键技术支撑,对高校人才培养提出更高要求。首先分析当前微处理器设计课程在教学内容、育人模式、实践环节等方面的现状与痛点,针对性提出课程教学改革思路;进而从基于RISC-V架构重构优化教学内容、强化课程思政引领以激发学生创新思维与家国情怀、完善实践教学体系并深度融入AI辅助编程技术3个维度,系统阐述教学改革实践路径;最后说明教改实施成效,为新工科背景下微处理器设计类课程的创新教学提供参考。 展开更多
关键词 人工智能 微处理器设计 RISC-V架构 蜂鸟E200处理器 AI辅助编程
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An Inference Microprocessor Design 认领 引用
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作者 沈绪榜 马光悌 陈岚 《Journal of Computer Science & Technology》 SCIE EI 1991年第3期209-213,共5页
This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various ... This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various production rule systems.The methods of translating linguistically expressed rules into nu- merical representations are described and the hardware implementations are discussed.Finally,a parallel architecture for the inference microprocessor is presented. 展开更多
关键词 In An Inference Microprocessor Design length
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A light-powered sub-threshold microprocessor 认领 引用
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作者 刘鸣 陈虹 +2 位作者 张春 李长猛 王志华 《Journal of Semiconductors》 EI CAS 北大核心 2010年第11期72-77,共6页
This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the... This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW,dynamic power of 385 nW @ 165 kHz,EDP 13 pJ/inst and the operating voltage of 350 mV are achieved.Under a light of about 150 kLux,the microprocessor can run at a rate of up to 500 kHz.The microprocessor can be used for wireless-sensor-network nodes 展开更多
关键词 power harvesting wireless-sensor-network sub-threshold microprocessor photosensitive diode
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