期刊文献+
任意字段
题名或关键词
题名
关键词
摘要
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息
共找到511篇文章
< 1 2 … 26 >
每页显示 20 50 100
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
显示方式：
Anti-Interference High-Speed Modulation Decoder for Quantum Key Distribution 认领 引用 被引量：1
1
作者 Hua-Xing Xu Shao-Hua Wang +1 位作者 Chang-Lei Wang Ping Zhang 《Chinese Physics Letters》 SCIE EI CAS CSCD 2025年第1期34-39,共6页
Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environ... Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices. 展开更多
关键词 decoder interferometer polarization
暂未订购 下载PDF
Design of improved error-rate sliding window decoder for SC-LDPC codes: reliable termination and channel value reuse 认领 引用
2
作者 JIA Xishan LI Jining +3 位作者 YAO Yuan WANG Yifan LIU Bo XU Degang 《Optoelectronics Letters》 EI 2025年第4期212-217,共6页
In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes u... In this paper,an improved error-rate sliding window decoder is proposed for spatially coupled low-density parity-check(SC-LDPC)codes.For the conventional sliding window decoder,the message retention mechanism causes unreliable messages along the edges of belief propagation(BP)decoding in the current window to be kept for subsequent window decoding.To improve the reliability of the retained messages during the window transition,a reliable termination method is embedded,where the retained messages undergo more reliable parity checks.Additionally,decoding failure is unavoidable and even causes error propagation when the number of errors exceeds the error-correcting capability of the window.To mitigate this problem,a channel value reuse mechanism is designed,where the received channel values are utilized to reinitialize the window.Furthermore,considering the complexity and performance of decoding,a feasible sliding optimized window decoding(SOWD)scheme is introduced.Finally,simulation results confirm the superior performance of the proposed SOWD scheme in both the waterfall and error floor regions.This work has great potential in the applications of wireless optical communication and fiber optic communication. 展开更多
关键词 reliable termination message retention mechanism reliable termination method sliding window decoderthe error rate sliding window decoder belief propagation bp decoding retained messages
暂未订购 下载PDF
Pyramid–MixNet: Integrate Attention into Encoder-Decoder Transformer Framework for Automatic Railway Surface Damage Segmentation 认领 引用
3
作者 Hui Luo Wenqing Li Wei Zeng 《Computers, Materials & Continua》 SCIE EI 2025年第7期1567-1580,共14页
Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi... Rail surface damage is a critical component of high-speed railway infrastructure,directly affecting train operational stability and safety.Existing methods face limitations in accuracy and speed for small-sample,multi-category,and multi-scale target segmentation tasks.To address these challenges,this paper proposes Pyramid-MixNet,an intelligent segmentation model for high-speed rail surface damage,leveraging dataset construction and expansion alongside a feature pyramid-based encoder-decoder network with multi-attention mechanisms.The encoding net-work integrates Spatial Reduction Masked Multi-Head Attention(SRMMHA)to enhance global feature extraction while reducing trainable parameters.The decoding network incorporates Mix-Attention(MA),enabling multi-scale structural understanding and cross-scale token group correlation learning.Experimental results demonstrate that the proposed method achieves 62.17%average segmentation accuracy,80.28%Damage Dice Coefficient,and 56.83 FPS,meeting real-time detection requirements.The model’s high accuracy and scene adaptability significantly improve the detection of small-scale and complex multi-scale rail damage,offering practical value for real-time monitoring in high-speed railway maintenance systems. 展开更多
关键词 Pyramid vision transformer encoder–decoder architecture railway damage segmentation masked multi-head attention mix-attention
暂未订购 下载PDF
Global receptive field transformer decoder method on quantum surface code data and syndrome error correction 认领 引用 被引量：1
4
作者 Ao-Qing Li Ce-Wen Tian +2 位作者 Xiao-Xuan Xu Hong-Yang Ma Jun-Qing Liang 《Chinese Physics B》 SCIE EI CAS CSCD 2025年第3期267-276,共10页
Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in cu... Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes. 展开更多
关键词 quantum error correction surface code transformer decoder
暂未订购 下载PDF
Low power Viterbi decoder design for low altitude adhoc networks 认领 引用
5
作者 FEI Yingying XIAO Chunlu +3 位作者 JING Wenhao MA Tianming WANG Jiahan JIN Jie 《High Technology Letters》 EI CAS 2025年第2期154-163,共10页
With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutio... With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder. 展开更多
关键词 low altitude adhoc network Manhattan distance network protocol Viterbi decoder field programmable gate array(FPGA)
暂未订购 下载PDF
Rethinking the Encoder-decoder Structure in Medical Image Segmentation from Releasing Decoder Structure 认领 引用 被引量：1
6
作者 Jiajia Ni Wei Mu +1 位作者 An Pan Zhengming Chen 《Journal of Bionic Engineering》 SCIE EI CSCD 2024年第3期1511-1521,共11页
Medical image segmentation has witnessed rapid advancements with the emergence of encoder-decoder based methods.In the encoder-decoder structure,the primary goal of the decoding phase is not only to restore feature ma... Medical image segmentation has witnessed rapid advancements with the emergence of encoder-decoder based methods.In the encoder-decoder structure,the primary goal of the decoding phase is not only to restore feature map resolution,but also to mitigate the loss of feature information incurred during the encoding phase.However,this approach gives rise to a challenge:multiple up-sampling operations in the decoder segment result in the loss of feature information.To address this challenge,we propose a novel network that removes the decoding structure to reduce feature information loss(CBL-Net).In particular,we introduce a Parallel Pooling Module(PPM)to counteract the feature information loss stemming from conventional and pooling operations during the encoding stage.Furthermore,we incorporate a Multiplexed Dilation Convolution(MDC)module to expand the network's receptive field.Also,although we have removed the decoding stage,we still need to recover the feature map resolution.Therefore,we introduced the Global Feature Recovery(GFR)module.It uses attention mechanism for the image feature map resolution recovery,which can effectively reduce the loss of feature information.We conduct extensive experimental evaluations on three publicly available medical image segmentation datasets:DRIVE,CHASEDB and MoNuSeg datasets.Experimental results show that our proposed network outperforms state-of-the-art methods in medical image segmentation.In addition,it achieves higher efficiency than the current network of coding and decoding structures by eliminating the decoding component. 展开更多
关键词 Medical image segmentation Encoder-decoder architecture Attention mechanisms Releasing decoder architecture Neural network
基于DCNv2和Transformer Decoder的隧道衬砌裂缝高效检测模型研究 认领 引用 被引量：9
7
作者 孙己龙 刘勇 +4 位作者 周黎伟 路鑫 侯小龙 王亚琼 王志丰 《图学学报》 CSCD 北大核心 2024年第5期1050-1061,共12页
为解决因衬砌裂缝性状随机、分布密集、标注框分辨率低所导致的现有模型识别精度低、检测速度慢及参数量庞大等问题,以第2版可变形卷积网络(DCNv2)和端到端变换器解码器(Transformer Decoder)为基础对YOLOv8网络框架进行改进,提出了面... 为解决因衬砌裂缝性状随机、分布密集、标注框分辨率低所导致的现有模型识别精度低、检测速度慢及参数量庞大等问题,以第2版可变形卷积网络(DCNv2)和端到端变换器解码器(Transformer Decoder)为基础对YOLOv8网络框架进行改进,提出了面向衬砌裂缝的检测模型DTD-YOLOv8。首先,通过引入DCNv2对YOLOv8主干卷积网络C2f进行融合以实现模型对裂缝形变特征的准确快速感知,同时采用Transformer Decoder对YOLOv8检测头进行替换以实现端到端框架内完整目标检测流程,从而消除因Anchor-free处理模式所带来的计算消耗。采用自建裂缝数据集对SSD,Faster-RCNN,RT-DETR,YOLOv3,YOLOv5,YOLOv8和DTD-YOLOv8的7种检测模型进行对比验证。结果表明:改进模型F1分数和mAP@50值分别为87.05%和89.58%;其中F1分数相较其他6种模型分别提高了14.16%,7.68%,1.55%,41.36%,8.20%和7.40%;mAP@50分别提高了28.84%,15.47%,1.33%,47.65%,10.14%和10.84%。改进模型参数量仅为RT-DETR的三分之一,检测单张图片的速度为16.01 ms,FPS为65.46帧每秒,对比其他模型检测速度得到提升。该模型在面向运营隧道裂缝检测任务需求时能够表现出高效的性能。 展开更多
关键词 隧道工程 目标检测 第2版可变形卷积网络 Transformer Decoder 衬砌裂缝
暂未订购 下载PDF
Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication 认领 引用 被引量：4
8
作者 WANG Yongqing LIU Donglei +1 位作者 SUN Lida WU Siliang 《China Communications》 SCIE CSCD 2014年第12期94-104,共11页
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)... In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction. 展开更多
关键词 quasi—cyclic code LDPC decoder m in-sum algorithm partial parallel structure lookup table
暂未订购 下载PDF
Determination of quantum toric error correction code threshold using convolutional neural network decoders 认领 引用 被引量：3
9
作者 Hao-Wen Wang Yun-Jia Xue +2 位作者 Yu-Lin Ma Nan Hua Hong-Yang Ma 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第1期136-142,共7页
Quantum error correction technology is an important solution to solve the noise interference generated during the operation of quantum computers.In order to find the best syndrome of the stabilizer code in quantum err... Quantum error correction technology is an important solution to solve the noise interference generated during the operation of quantum computers.In order to find the best syndrome of the stabilizer code in quantum error correction,we need to find a fast and close to the optimal threshold decoder.In this work,we build a convolutional neural network(CNN)decoder to correct errors in the toric code based on the system research of machine learning.We analyze and optimize various conditions that affect CNN,and use the RestNet network architecture to reduce the running time.It is shortened by 30%-40%,and we finally design an optimized algorithm for CNN decoder.In this way,the threshold accuracy of the neural network decoder is made to reach 10.8%,which is closer to the optimal threshold of about 11%.The previous threshold of 8.9%-10.3%has been slightly improved,and there is no need to verify the basic noise. 展开更多
关键词 quantum error correction toric code convolutional neural network(CNN)decoder
暂未订购 下载PDF
Area optimization of parallel Chien search architecture for Reed-Solomon(255,239) decoder 认领 引用 被引量：2
10
作者 胡庆生 王志功 +1 位作者 张军 肖洁 《Journal of Southeast University(English Edition)》 EI CAS 2006年第1期5-10,共6页
A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） mult... A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved. 展开更多
关键词 RS decoder Chien search circuit area optimization Galois field multiplier
暂未订购 下载PDF
Efficient VLSI architecture of CAVLC decoder with power optimized 认领 引用 被引量：3
11
作者 陈光化 胡登基 +2 位作者 张金艺 郑伟峰 曾为民 《Journal of Shanghai University(English Edition)》 2009年第6期462-465,共4页
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design... This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard. 展开更多
关键词 H.264/advanced video coding （AVC） contest-based adaptive variable length code （CAVLC） decoder
暂未订购 下载PDF
Hardware-Software Co-implementation of H.264 Decoder in SoC 认领 引用 被引量：1
12
作者 杨宇红 张文军 +1 位作者 熊恋学 饶振宁 《Journal of Shanghai Jiaotong university(Science)》 EI 2006年第3期335-339,共5页
With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW... With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility. 展开更多
关键词 HW-SW co-implementation single instruction multiple data （SIMD） multimedia processor H.264 decoder coprocessor
暂未订购 下载PDF
Image restoration of finger-vein networks based on encoder-decoder model 认领 引用 被引量：1
13
作者 GUO Xiao-jing LI Dan +1 位作者 ZHANG Hai-gang YANG Jin-feng 《Optoelectronics Letters》 EI 2019年第6期463-467,共5页
Finger-vein recognition is widely applied on access control system due to the high user acceptance and convince. Improving the integrity of finger-vein is helpful for increasing the finger-vein recognition accuracy. D... Finger-vein recognition is widely applied on access control system due to the high user acceptance and convince. Improving the integrity of finger-vein is helpful for increasing the finger-vein recognition accuracy. During the process of finger-vein imaging, foreign objects may be attached on fingers, which directly affects the integrity of finger-vein images. In order to effectively extract finger-vein networks, the integrity of venous networks is still not ideal after preprocessing of finger vein images. In this paper, we propose a novel deep learning based image restoration method to improve the integrity of finger-vein networks. First, a region detecting method based on adaptive threshold is presented to locate the incomplete region. Next, an encoder-decoder model is used to restore the venous networks of the finger-vein images. Then we analyze the restoration results using several different methods. Experimental results show that the proposed method is effective to restore the venous networks of the finger-vein images. 展开更多
关键词 decoder networks incomplete
暂未订购 下载PDF
A Total Dose Radiation Hardened PDSOI CMOS 3-Line to 8-Line Decoder 认领 引用
14
作者 刘梦新 韩郑生 +3 位作者 李多力 刘刚 赵超荣 赵发展 《Journal of Semiconductors》 CAS 北大核心 2008年第6期1036-1039,共4页
The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transisto... The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed. 展开更多
关键词 PDSOI decoder total dose radiation
暂未订购 下载PDF
A hardware/software co-optimization approach for embedded software of MP3 decoder 认领 引用
15
作者 ZHANG Wei LIU Peng ZHAI Zhi-bo 《Journal of Zhejiang University-SCIENCE A》 SCIE EI CAS 2007年第1期42-49,共8页
In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed st... In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture. 展开更多
关键词 Hardware/software co-optimization DSP Embedded software MP3 decoder
暂未订购 下载PDF
The Formal Specifications for Protocols of Decoders 认领 引用
16
作者 YUAN Meng-ting WU Guo-qing SHU Feng-di 《Wuhan University Journal of Natural Sciences》 EI CAS 2004年第6期879-882,共4页
This paper presents a formal approach,FSPD(Formal Specifications for Protocols of Decoders),to specify decoder communication protocols.Based on axiomatic,FSPD is a precise language with which programmers could use onl... This paper presents a formal approach,FSPD(Formal Specifications for Protocols of Decoders),to specify decoder communication protocols.Based on axiomatic,FSPD is a precise language with which programmers could use only one suitable driver to handle various types of decoders.FSPD is helpful for programmers to get high adaptability and reusability of decoder-driver software. 展开更多
关键词 formalization digital video security system protocol of decoders
暂未订购 下载PDF
PERFORMANCE ANALYSIS AND SIMULATION OF OCDMA SYSTEM BASED ON FBGs ENCODER/DECODER 认领 引用
17
作者 Li Chuanqi Sun Xiaohan Je-Myung Jeong 《Journal of Electronics(China)》 2005年第6期663-670,共8页
The encoding/decoding scheme based on Fiber Bragg Grating (FBG) for Optical Code Division Multiple Access (OCDMA) system is analyzed and the whole process from transmitting end to receiving end is researched in detail... The encoding/decoding scheme based on Fiber Bragg Grating (FBG) for Optical Code Division Multiple Access (OCDMA) system is analyzed and the whole process from transmitting end to receiving end is researched in detail. The mathematical mode including signal transmission, summing, receiving and recovering are established respectively. One of the main sources of Bit Error Rate (BER) of OCDMA system based on FBGs is the unevenness of signal power spectrum, which leads to the chip powers unequal with each other. The Signal to Interfere Ratio (SIR) and BER performance of the system are studied and simulated at the case with uneven distribution of chips' powers. 展开更多
关键词 Optical Code Division Multiple Access （OCDMA） Fiber Bragg Grating （FBG） Optical encoder/decoder
暂未订购 下载PDF
Design and implementation of an efficient SDRAM controller for HDTV decoder 认领 引用 被引量：3
18
作者 王晓辉 Zhao Yiqiang +2 位作者 Xie Xiaodong Wu Di Zhang Peng 《High Technology Letters》 EI CAS 2007年第4期402-406,共5页
A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces... A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz. 展开更多
关键词 SDRAM controller MB-based address mapping adaptive-precharge command interleaving HDTV decoder
暂未订购 下载PDF
Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications 认领 引用 被引量：1
19
作者 Zhen Gao Lina Yan +3 位作者 Jinhua Zhu Ruishi Han Ullah Anees Reviriego Pedro 《China Communications》 SCIE CSCD 2020年第1期140-150,共11页
Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,... Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations. 展开更多
关键词 viterbi decoder on-board processing FPGA user memory fault tolerance single event upsets
暂未订购 下载PDF
Construction of Quasi-Cyclic Low-Density Parity-Check Codes for Simplifying Shuffle Networks in Layered Decoder 认领 引用 被引量：1
20
作者 张建军 董明科 +2 位作者 王达 金野 项海格 《China Communications》 SCIE CSCD 2013年第12期102-113,共12页
Offset Shuffle Networks(OSNs) interleave a-posterior probability messages in the Block Row-Layered Decoder(BRLD) of QuasiCyclic Low-Density Parity-Check(QC-LDPC)codes.However,OSNs usually consume a significant amount ... Offset Shuffle Networks(OSNs) interleave a-posterior probability messages in the Block Row-Layered Decoder(BRLD) of QuasiCyclic Low-Density Parity-Check(QC-LDPC)codes.However,OSNs usually consume a significant amount of computational resources and limit the clock frequency,particularly when the size of the Circulant Permutation Matrix(CPM)is large.To simplify the architecture of the OSN,we propose a Simplified Offset Shuffle Network Block Progressive Edge-Growth(SOSNBPEG) algorithm to construct a class of QCLDPC codes.The SOSN-BPEG algorithm constrains the shift values of CPMs and the difference of the shift values in the same column by progressively appending check nodes.Simulation results indicate that the error performance of the SOSN-BPEG codes is the same as that of the codes in WiMAX and DVB-S2.The SOSNBPEG codes can reduce the complexity of the OSNs by up to 54.3%,and can improve the maximum frequency by up to 21.7%for various code lengths and rates. 展开更多
关键词 QC-LDPC codes construction alg-orithm PEG algorithm row-layered decoder shuffle network
暂未订购 下载PDF
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
上一页 1 2 … 26 下一页 到第 页
在线咨询 使用帮助 返回顶部 意见反馈