双有源桥变换器因其优异的功率密度和双向功率传输能力,在众多工业应用中得到广泛关注。随着电力电子设备对能效和可靠性要求的不断提高,双有源桥变换器的电流应力已成为衡量其性能的关键指标之一。过大的电流应力不仅会导致功率器件损...双有源桥变换器因其优异的功率密度和双向功率传输能力,在众多工业应用中得到广泛关注。随着电力电子设备对能效和可靠性要求的不断提高,双有源桥变换器的电流应力已成为衡量其性能的关键指标之一。过大的电流应力不仅会导致功率器件损耗增加,系统效率下降,还会影响变换器的可靠性和使用寿命。针对上述问题,提出了一种基于TabNet-LN-LSTM协同预测与粒子群优化的电流应力优化方法。该方法通过利用TabNet和层归一化长短期记忆神经网络(Long-short term memory neural network with layer normalization,LN-LSTM)协同构建电感电流时序预测模型,并结合粒子群优化算法对双有源桥变换器在不同运行工况下的电流应力进行优化。通过算法试验和硬件试验证明,所提方法不仅能够精确预测电感电流波形,其预测波形与硬件实测波形相比,其平均绝对误差仅为0.3525,决定系数高达97.17%;同时,能够有效降低双有源桥变换器的电流应力,进一步提升系统的整体效能和可靠性。展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
摘要双有源桥变换器因其优异的功率密度和双向功率传输能力,在众多工业应用中得到广泛关注。随着电力电子设备对能效和可靠性要求的不断提高,双有源桥变换器的电流应力已成为衡量其性能的关键指标之一。过大的电流应力不仅会导致功率器件损耗增加,系统效率下降,还会影响变换器的可靠性和使用寿命。针对上述问题,提出了一种基于TabNet-LN-LSTM协同预测与粒子群优化的电流应力优化方法。该方法通过利用TabNet和层归一化长短期记忆神经网络(Long-short term memory neural network with layer normalization,LN-LSTM)协同构建电感电流时序预测模型,并结合粒子群优化算法对双有源桥变换器在不同运行工况下的电流应力进行优化。通过算法试验和硬件试验证明,所提方法不仅能够精确预测电感电流波形,其预测波形与硬件实测波形相比,其平均绝对误差仅为0.3525,决定系数高达97.17%;同时,能够有效降低双有源桥变换器的电流应力,进一步提升系统的整体效能和可靠性。
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
摘要This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.