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Thread Private Variable Access Optimization Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Jinying Kong Kai Nie +2 位作者 Qinglei Zhou Jinlong Xu Lin Han 《国际计算机前沿大会会议论文集》 EI 2021年第1期180-189,共10页
The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow acce... The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow accessto thread private variables in the compilation of Sunway OpenMP programs, thispaper proposes a thread private variable access technique based on privilegedinstructions. The privileged instruction-based thread-private variable access techniquecentralizes the implementation of thread-private variables at the compilerlevel, eliminating the model switching overhead of invoking OS core processingand improving the speed of accessing thread-private variables. On the Sunway1621 server platform, NPB3.3-OMP and SPEC OMP2012 achieved 6.2% and6.8% running efficiency gains, respectively. The results show that the techniquesproposed in this paper can provide technical support for giving full play to theadvantages of Sunway’s high-performance multi-core processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Privileged instruction-based thread-private variable access technique Sunway 1621 processor
Parallel Region Reconstruction Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Kai Nie Qinglei Zhou +3 位作者 Hong Qian Jianmin Pang Jinlong Xu Yapeng Li 《国际计算机前沿大会会议论文集》 EI 2021年第1期163-179,共17页
The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by hight... The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by highthread group control overhead in the compilation of Sunway OpenMP programs,this paper proposes the parallel region reconstruction technique. The parallelregion reconstruction technique expands the parallel scope of parallel regionsin OpenMP programs by parallel region merging and parallel region extending.Moreover, it reduces the number of parallel regions in OpenMP programs,decreases the overhead of frequent creation and convergence of thread groups,and converts standard fork-join model OpenMP programs to higher performanceSPMD modelOpenMP programs. On the Sunway 1621 server computer, NPB3.3-OMP and SPEC OMP2012 achieved 8.9% and 7.9% running efficiency improvementrespectively through parallel region reconstruction technique. As a result,the parallel region reconstruction technique is feasible and effective. It providestechnical support to fully exploit the multi-core parallelism advantage of Sunway’shigh-performance processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Parallel domain reconstruction technique
Research on Multi-Core Processor Analysis for WCET Estimation 认领 引用
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作者 LUO Haoran HU Shuisong +2 位作者 WANG Wenyong TANG Yuke ZHOU Junwei 《ZTE Communications》 2024年第1期87-94,共8页
Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardwar... Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field. 展开更多
关键词 real-time system worst-case execution time(WCET) multi-core analysis
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Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors 认领 引用
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作者 Muhammad Ali Ismail 《Computer Technology and Application》 2012年第11期729-733,共5页
In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core proces... In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper. 展开更多
关键词 Multi-core memory hierarchy cache access time queuing analysis.
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Design and optimization of weakly coupled multi-core fiber 认领 引用
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作者 ZHAN Yi WANG An +1 位作者 ZHANG Qing-long WANG Yi-han 《中国光学（中英文）》 EI CAS CSCD 北大核心 2026年第3期730-744,共15页
In order to achieve comprehensive,highly efficient,and multi-objective precise optimization of fiber structural parameters and further enhance the transmission capacity of optical communication systems,a homogeneous w... In order to achieve comprehensive,highly efficient,and multi-objective precise optimization of fiber structural parameters and further enhance the transmission capacity of optical communication systems,a homogeneous weakly coupled seven-core fiber based on trench-assisted structures is designed.Particle Swarm Optimization(PSO)is introduced to replace traditional empirical designs or local scanning methods.First,a multi-objective fitness function incorporating constraints such as dispersion,cutoff wavelength,ef-fective mode field area,and coating loss is established.Then,the algorithm performs a global search to pre-cisely determine the optimal structural parameters under standard dimensional constraints.Simulation results demonstrate that with a fiber core pitch of 45μm,the optimized fiber achieves an ultra-low inter-core crosstalk of below−90 dB/km at a wavelength of 1550 nm.This design scheme not only effectively resolves the conflict between crosstalk suppression and spatial utilization in multi-core fibers but also proves the effi-ciency and reliability of the PSO algorithm in complex fiber structural design,providing an important theor-etical basis and technical support for the research and manufacturing of ultra-large-capacity optical commu-nication systems. 展开更多
关键词 multi-core fiber particle swarm optimization trench-assisted inter-core crosstalk space divi-sion multiplexing
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Heterogeneous multi-core task scheduling based on adaptive simulated annealing 认领 引用
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作者 ZHU Guoliang ZHANG Jinjian +4 位作者 LIU Xuan WANG Guojun ZHANG Xiaodong CHEN Kaiyu WANG Yu 《Journal of Systems Engineering and Electronics》 SCIE CSCD 2026年第3期897-903,共7页
To address the energy consumption issues caused by task lengths in task scheduling on heterogeneous multi-core systems,this paper proposes an adaptive parameterized improved simulated annealing algorithm based on the ... To address the energy consumption issues caused by task lengths in task scheduling on heterogeneous multi-core systems,this paper proposes an adaptive parameterized improved simulated annealing algorithm based on the directed acyclic graph task model.The algorithm employs feedback from acceptance rates to dynamically adjust the temperature and neighborhood size of the simulated annealing process.Additionally,it introduces a security mechanism to enhance convergence speed and global search capabilities.Compared against classical simulated annealing and standard heuristic algorithms,the proposed algorithm achieves reductions exceeding 54% in convergence generations,50% in task slots,and 10% in scheduling time,providing a direction for low-power task scheduling. 展开更多
关键词 heterogeneous multi-core task scheduling schedule length simulated annealing
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System Architecture of Godson-3 Multi-Core Processors 认领 引用 被引量：19
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作者 高翔 陈云霁 +2 位作者 王焕东 唐丹 胡伟武 《Journal of Computer Science & Technology》 SCIE EI 2010年第2期181-191,共11页
Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This pa... Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This paper introduces the system architecture of Godson-3 from various aspects including system scalability, organization of memory hierarchy, network-on-chip, inter-chip connection and I/O subsystem. 展开更多
关键词 multi-core processor scalable interconnection cache coherent non-uniform memory accesson-uniform cache access （CC-NUMA/NUCA） MESH crossbar cache coherence reliability availability and serviceability （RAS）
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Parallel computing of discrete element method on multi-core processors 认领 引用 被引量：7
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作者 Yusuke Shigeto Mikio Sakai 《Particuology》 SCIE EI CAS CSCD 2011年第4期398-405,共8页
This paper describes parallel simulation techniques for the discrete element method （DEM） on multi-core processors. Recently, multi-core CPU and GPU processors have attracted much attention in accelerating computer ... This paper describes parallel simulation techniques for the discrete element method （DEM） on multi-core processors. Recently, multi-core CPU and GPU processors have attracted much attention in accelerating computer simulations in various fields. We propose a new algorithm for multi-thread parallel computation of DEM, which makes effective use of the available memory and accelerates the computation. This study shows that memory usage is drastically reduced by using this algorithm. To show the practical use of DEM in industry, a large-scale powder system is simulated with a complicated drive unit. We compared the performance of the simulation between the latest GPU and CPU processors with optimized programs for each processor. The results show that the difference in performance is not substantial when using either GPUs or CPUs with a multi-thread parallel algorithm. In addition, DEM algorithm is shown to have high scalabilitv in a multi-thread parallel computation on a CPU. 展开更多
关键词 Discrete element method Parallel computing Multi-core processor GPGPU
Multi-core optimization for conjugate gradient benchmark on heterogeneous processors 认领 引用
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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MT-office:parallel password recovery program for office on domestic heterogeneous multi-core processor 认领 引用 被引量：2
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作者 Yongtao Luo Bo Yang +5 位作者 Jie Liu Ruibo Wang Jinmin Wen Tiaojie Xiao Xuguang Chen Chunye Gong 《CCF Transactions on High Performance Computing》 EI 2023年第3期231-244,共14页
With the improvement of security awareness,in order to guarantee information security,more advanced and secure encryption algorithms are applied to Microsoft Office.People also set more complex encryption passwords.Ho... With the improvement of security awareness,in order to guarantee information security,more advanced and secure encryption algorithms are applied to Microsoft Office.People also set more complex encryption passwords.However,once the initial password is forgotten,the encrypted information needs to be retrieved.The conventional brute force cracking methods and password recovery programs can hardly meet the actual deciphering needs.To this end,we develop a distributed parallel password recovery program(MT-Office)for Microsoft Office on the domestic heterogeneous multi-core processor(MT-3000).MT-Office takes full advantage of the multi-core and heterogeneous features of MT-3000,and is optimized and improved in both vectorization and global computing.At the same time,MT-Office provides multiple recovery strategies in password generation to improve the recovery efficiency.Compared with other platforms(e.g.,Intel platforms and FT platforms),MT-3000 heterogeneous platform can achieve 60×–218×speedup ratio.For Office2010,we perform a strong scalability test on the new-generation supercomputer in National Supercomputer Center in Tianjin.MT-Office not only extends to 65,536 acceleration clusters on this system,shows good scalability,but also achieves almost linear speedup ratio.For Office2007,compared with other password recovery programs,MT-Office can achieve 2.5×–131.1×speedup ratio.It can be seen that MT-Office can better exploit the advantages of MT-3000,which not only has good scalability and parallelism,but also has faster deciphering speed and can be applied to practical engineering application. 展开更多
关键词 Office password recovery Heterogeneous multi-core processor SIMD Heterogeneous computing
Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity 认领 引用 被引量：1
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作者 Zhi-xiang CHEN Zhao-lin LI +2 位作者 Shan CAO Fang WANG Jie ZHOU 《Frontiers of Information Technology & Electronic Engineering》 SCIE EI CSCD 2015年第12期1018-1033,共16页
Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturin... Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations,can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining(HASR) scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains.We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme,representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%. 展开更多
关键词 Schedule refining Multi-core processor Heterogeneity Representative chip operating point
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Energy Efficiency of a Multi-Core Processor by Tag Reduction 认领 引用
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作者 郑龙 董冕雄 +3 位作者 Kaoru Ota 金海 Song Guo 马俊 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第3期491-503,共13页
We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This p... We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor. 展开更多
关键词 tag reduction multi-core processor energy efficiency
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An efficient geosciences workflow on multi-core processors and GPUs:a case study for aerosol optical depth retrieval from MODIS satellite data 认领 引用 被引量：3
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作者 Jia Liu Dustin Feld +3 位作者 Yong Xue Jochen Garcke Thomas Soddemann Peiyuan Pan 《International Journal of Digital Earth》 SCIE EI CSCD 2016年第8期748-765,共18页
Quantitative remote sensing retrieval algorithms help understanding the dynamic aspects of Digital Earth.However,the Big Data and complex models in Digital Earth pose grand challenges for computation infrastructures.I... Quantitative remote sensing retrieval algorithms help understanding the dynamic aspects of Digital Earth.However,the Big Data and complex models in Digital Earth pose grand challenges for computation infrastructures.In this article,taking the aerosol optical depth(AOD)retrieval as a study case,we exploit parallel computing methods for high efficient geophysical parameter retrieval.We present an efficient geocomputation workflow for the AOD calculation from the Moderate Resolution Imaging Spectroradiometer(MODIS)satellite data.According to their individual potential for parallelization,several procedures were adapted and implemented for a successful parallel execution on multicore processors and Graphics Processing Units(GPUs).The benchmarks in this paper validate the high parallel performance of the retrieval workflow with speedups of up to 5.x on a multi-core processor with 8 threads and 43.x on a GPU.To specifically address the time-consuming model retrieval part,hybrid parallel patterns which combine the multicore processor’s and the GPU’s compute power were implemented with static and dynamic workload distributions and evaluated on two systems with different CPU–GPU configurations.It is shown that only the dynamic hybrid implementation leads to a greatly enhanced overall exploitation of the heterogeneous hardware environment in varying circumstances. 展开更多
关键词 Digital earth highperformance computing GPU multi-core hybrid parallel pattern aerosol optical depth retrieval workflow
Adaptive data-driven parallelization of multi-view video coding on multi-core processor 认领 引用 被引量：2
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作者 PANG Yi HU WeiDong +1 位作者 SUN LiFeng YANG ShiQiang 《Science in China(Series F)》 2009年第2期195-205,共11页
Multi-view video coding(MVC)comprises rich 3D information and is widely used in new visual media,such as 3DTV and free viewpoint TV(FTV).However,even with mainstream computer manufacturers migrating to multi-core proc... Multi-view video coding(MVC)comprises rich 3D information and is widely used in new visual media,such as 3DTV and free viewpoint TV(FTV).However,even with mainstream computer manufacturers migrating to multi-core processors,the huge computational requirement of MVC currently prohibits its wide use in consumer markets.In this paper,we demonstrate the design and implementation of the first parallel MVC system on Cell Broadband Engine^TM processor which is a state-of-the-art multi-core processor.We propose a task-dispatching algorithm which is adaptive data-driven on the frame level for MVC,and implement a parallel multi-view video decoder with modified H.264/AVC codec on real machine.This approach provides scalable speedup(up to 16 times on sixteen cores)through proper local store management,utilization of code locality and SIMD improvement.Decoding speed,speedup and utilization rate of cores are expressed in experimental results. 展开更多
关键词 adaptive data-driven multi-view video coding Cell Broadband Engine^TM Processor parallelization
Resources Snapshot Model for Concurrent Transactions in Multi-Core Processors 认领 引用
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作者 赵雷 杨季文 《Journal of Computer Science & Technology》 SCIE EI CSCD 2013年第1期106-118,共13页
Transaction parallelism in database systems is an attractive way of improving transaction performance. There exists two levels of transaction parallelism, inter-transaction level and intra-transaction level. With the ... Transaction parallelism in database systems is an attractive way of improving transaction performance. There exists two levels of transaction parallelism, inter-transaction level and intra-transaction level. With the advent of multi- core processors, new hopes of improving transaction parallelism appear on the scene. The greatest execution efficiency of concurrent transactions comes from the lowest dependencies of them. However, the dependencies of concurrent transactions stand in the way of exploiting parallelism. In this paper, we present Resource Snapshot Model （RSM） for resource modeling in both levels. We propose a non-restarting scheduling algorithm in the inter-transaction level and a processor assignment algorithm in the intra-transaction level in terms of multi-core processors. Through these algorithms, execution performance of transaction streams will be improved in a parallel system with multiple heterogeneous processors that have different number of cores. 展开更多
关键词 multi-core database transaction parallelism concurrency conflict detection
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Preparation and sustained release performance of multi-core capsules based on fragrance-loaded Pickering emulsions 认领 引用
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作者 Xinyi Liu Juanbo Chen +4 位作者 Haoyue Hou Jiawei Hou Meiling Shi Sa Zeng Tao Meng 《日用化学工业（中英文）》 CAS 北大核心 2025年第3期286-294,共9页
Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragran... Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragranceloaded capsules.In this work,the natural materials sodium alginate and gelatine are dissolved and act as the aqueous phase,lavender is dissolved in caprylic/capric triglyceride(GTCC)as the oil phase,and SiO2 nanoparticles with neutralwettability as a solid emulsifier to form O/W Pickering emulsions simultaneously.Finally,multi-core capsules are prepared using the drop injection method with emulsions as templates.The results show that the capsules have been successfully prepared with a spherical morphology and multi-core structure,and the encapsulation rate of multi-core capsules can reach up to 99.6%.In addition,the multi-core capsules possess desirable sustained release performance,the cumulative sustained release rate of fragrance at 25℃over 49 days is only 32.5%.It is attributed to the significant protection of multi-core structure,Pickering emulsion nanoparticle membranes,and hydrogel network shell for encapsulated fragrance.This study is designed to deliver a new strategy for using sustained-release technology with fragrance in food,cosmetics,textiles,and other fields. 展开更多
关键词 fragrance Pickering emulsion multi-core capsules encapsulation efficiency sustained release
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A heuristic mixed real-time task allocation of virtual utilization in multi-core processor 认领 引用 被引量：4
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作者 Hongbiao Liu Mengfei Yang +3 位作者 Tingyu Wang Chenghao Song Shenghui Zhu Xi Chen 《Journal of Information and Intelligence》 2023年第2期156-177,共22页
Multi-core processor is widely used as the running platform for safety-critical real-time systems such as spacecraft,and various types of real-time tasks are dynamically added at runtime.In order to improve the utiliz... Multi-core processor is widely used as the running platform for safety-critical real-time systems such as spacecraft,and various types of real-time tasks are dynamically added at runtime.In order to improve the utilization of multi-core processors and ensure the real-time performance of the system,it is necessary to adopt a reasonable real-time task allocation method,but the existing methods are only for single-core processors or the performance is too low to be applicable.Aiming at the task allocation problem when mixed real-time tasks are dynamically added,we propose a heuristic mixed real-time task allocation algorithm of virtual utilization VU-WF(Virtual Utilization Worst Fit)in multi-core processor.First,a 4-tuple task model is established to describe the fixedpoint task and the sporadic task in a unified manner.Then,a VDS(Virtual Deferral Server)for serving execution requests of fixed-point task is constructed and a schedulability test of the mixed task set is derived.Finally,combined with the analysis of VDS's capacity,VU-WF is proposed,which selects cores in ascending order of virtual utilization for the schedulability test.Experiments show that the overall performance of VU-WF is better than available algorithms,not only has a good schedulable ratio and load balancing but also has the lowest runtime overhead.In a 4-core processor,compared with available algorithms of the same schedulability ratio,the load balancing is improved by 73.9%,and the runtime overhead is reduced by 38.3%.In addition,we also develop a visual multi-core mixed task scheduling simulator RT-MCSS(open source)to facilitate the design and verification of multi-core scheduling for users.As the high performance,VU-WF can be widely used in resource-constrained and safety-critical real-time systems,such as spacecraft,self-driving cars,industrial robots,etc. 展开更多
关键词 Mixed real-time task set Multi-core scheduling Task dynamical adding Virtual utilization Scheduling simulator
NeuroPulse:Spiking-Transformer Hybrid Architecture for Ultra-Low-Power Continual Learning in Neuromorphic Network Processors 认领 引用
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作者 Mohammed Abdullah Alsuwaiket 《Computers, Materials & Continua》 SCIE EI 2026年第9期1735-1757,共23页
Conventional deep learning networks impose prohibitive energy requirements on continuously operational network intelligence applications such as anomaly detection,traffic classification,and adaptive Quality-of-Service... Conventional deep learning networks impose prohibitive energy requirements on continuously operational network intelligence applications such as anomaly detection,traffic classification,and adaptive Quality-of-Service(QoS)control.This paper proposes NeuroPulse,a spiking-transformer hybrid neural architecture that combines the temporal sparsity of spiking neural networks(SNNs)with the representational power of sparse self-attention,enabling efficient deployment on neuromorphic network processors(NNPs).We propose a Rate-Coded Cross-Attention(RCCA)module,which converts population-coded spike-trains into attention queries,allowing long-range dependency modeling within sub-milliwatt(sub-mW)power budgets.NeuroPulse also supports catastrophe-free continual learning on non-stationary network traffic distributions via a Hebbian Synaptic Consolidation(HSC)mechanism,eliminating the need for full model retraining.Experiments on NSL-KDD,UNSW-NB15,and real-world 5G RAN telemetry datasets demonstrate that NeuroPulse achieves 94.3%intrusion detection accuracy at 0.23 mW average energy consumption—a 12×power reduction over transformer-only baselines—while retaining 97.1%of accumulated knowledge after 50 sequential task updates,making it uniquely suited for always-on intelligent network nodes. 展开更多
关键词 Spiking neural networks neuromorphic computing sparse self-attention continuous learning intrusion detection energy efficient AI network processors
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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture 认领 引用
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作者 Allam Abumwais Mahmoud Obaid 《Computers, Materials & Continua》 SCIE EI 2023年第3期4951-4963,共13页
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc... Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors. 展开更多
关键词 Multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program
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Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment 认领 引用
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作者 郭明强 Huang Ying Xie Zhong 《High Technology Letters》 EI CAS 2014年第4期395-400,共6页
In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of pa... In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained. 展开更多
关键词 parallel scheduling strategy the web-based spatial computing model multi-core environment load balancing
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