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Principle and Implementation of an MC4044-Based Phase Locked Loop for Constant Speed Control 认领 引用 被引量：3
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作者 孙国富 顾启泰 刘学斌 《Tsinghua Science and Technology》 CAS 2000年第4期409-413,共5页
An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration... An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[ 展开更多
关键词 MC4044 phase locked loop DC motor constant speed contro?
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A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop 认领 引用 被引量：2
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作者 Tao Deng Mao-Li Ma +1 位作者 Qing-Hui Liu Ya-Jun Wu 《Research in Astronomy and Astrophysics》 SCIE CAS CSCD 2021年第9期83-90,共8页
In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points... In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved. 展开更多
关键词 Doppler frequency measurement:deep space exploration:carrier tracking:phase locked loop:high precision
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Low phase noise millimeter wave monolithic integrated phase locked-loop 认领 引用
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作者 Tang Lu Wang Zhigong Qiu Yinghua Xu Jian 《High Technology Letters》 EI CAS 2012年第3期263-266,共4页
A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The ... A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds. 展开更多
关键词 phase locked loop （PLL） voltage-controlled oscillator （VCO） coplanarwaveguides （CPWs） GaAs
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THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS 认领 引用
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作者 Deng Xiaoying Yang Jun Shi Longxing Chen Xin 《Journal of Electronics(China)》 2008年第5期673-678,共6页
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change... A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz. 展开更多
关键词 All-Digital Phase Locked Loop （ADPLL） Digital Controlled Oscillator （DCO） Impulse Sensitivity Function （ISF） Thermal noise Jitter
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Realization of Highly Reliable 10-20-Level Instability Optical Phase Transmission over a 1402-Kilometer Commercial Fiber-Optic Network 认领 引用
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作者 Yang Xu Libo Li +5 位作者 Kan Zhao Pingan Ma Zhiwei Zhang Qi Shen Faxi Chen Haifeng Jiang 《Chinese Physics Letters》 SCIE EI CAS CSCD 2025年第12期84-88,共5页
Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventiona... Optical phase transfer via fiber optics is the most effective method for optical frequency standard comparison on the scale below thousands of kilometers.However,the monotonic phase discrimination range of conventional optical phase-locked loops is limited,and link delays restrict the control bandwidth,which makes it a challenge to achieve a continuously reliable optical link.This paper presents an event-timing-based phase detection method that overcomes the monotonic phase discrimination range limitation of conventional phase-locked loops through dual-edge timestamp recording,achieving an optical phase measurement resolution on the order of 10 attoseconds.With such a technique,we established a 7-segment-cascaded optical link over 1402km of commercial fiber while sharing dense wavelength division multiplexing(DWDM)channels with live telecom traffic.The system maintained continuous operation for 11.7 days without phase cycle slips despite encountering 15 km aerial fiber noise up to 21000 rad2·Hz−1·km−1at 1 Hz.Relative instabilities of the link are 3.7×10−15at 1 s and 3.9×10−20at 100000 s. 展开更多
关键词 fiber optics optical phase locked loops optical phase transfer event timing based phase detection link delays commercial fiber optic network optical frequency standard comparison monotonic phase discrimination range
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Small-signal Stability of Grid-connected Converter System in Renewable Energy Systems with Fractional-order Synchronous Reference Frame Phase-locked Loop 认领 引用
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作者 Peng Zhang Wenjuan Du Haifeng Wang 《Journal of Modern Power Systems and Clean Energy》 SCIE EI CSCD 2025年第3期1090-1101,共12页
Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchro... Fractional-order control(FOC)has gained significant attention in power system applications due to their ability to enhance performance and increase stability margins.In grid-connected converter(GCC)systems,the synchronous reference frame phase-locked loop(SRF-PLL)plays a critical role in grid synchronization for renewable power generation.However,there is a notable research gap regarding the application of FOC to the SRF-PLL.This paper proposes a fractional-order SRF-PLL(FO-SRF-PLL)that incorporates FOC to accurately track the phase angle of the terminal voltage,thereby improving the efficiency of grid-connected control.The dynamic performance of the proposed FO-SRF-PLL is evaluated under varying grid conditions.A comprehensive analysis of the small-signal stability of the GCC system employing the FO-SRF-PLL is also presented,including derived small-signal stability conditions.The results demonstrate that the FO-SRF-PLL significantly enhances robustness against disturbances compared with the conventional SRF-PLL.Furthermore,the GCC system with the FO-SRF-PLL maintains stability even under weak grid conditions,showing superior stability performance over the SRF-PLL.Finally,both simulation and experimental results are provided to validate the analysis and conclusions presented in this paper. 展开更多
关键词 Small-signal stability grid-connected converter(GCC)system fractional-order control(FOC) fractional-order synchronous reference frame phase locked loop(FO-SRF-PLL)
Sensorless Speed Control of Synchronous Reluctance Motor Using an Advanced Fictitious Flux Estimation Including Cross Coupling Effect 认领 引用
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作者 Abdin Abdin Nicola Bianchi +3 位作者 Andrea Voltan Walter Faedo Piero Cazzavillan Alessandro Biason 《Energy Engineering》 EI 2026年第3期481-495,共15页
Synchronous reluctance motors(SynRM)are widely employed in industrial applications due to their high robustness,low cost,and absence of permanent magnets.In recent years,significant research efforts have focused on im... Synchronous reluctance motors(SynRM)are widely employed in industrial applications due to their high robustness,low cost,and absence of permanent magnets.In recent years,significant research efforts have focused on improving the controllability and efficiency of SynRM.Accurate rotor position information is essential for the controller to generate appropriate current and voltage references corresponding to the desired speed and load torque.Shaft-mounted position sensors are generally undesirable because of their high cost,sensitivity to harsh operating conditions,maintenance requirements,and reduced reliability in environments characterized by high vibration.Consequently,sensorless control techniques that estimate rotor position using measured stator currents and voltages have attracted increasing attention.However,magnetic saturation,parameter nonlinearities,and cross-coupling effects significantly degrade position estimation accuracy and may compromise the stability of sensorless SynRM drives.In this paper,a nonlinear SynRM model is developed using finite element analysis(FEA)to accurately capture magnetic saturation and cross-coupling effects,thereby providing a precise representation of the machine’s electromagnetic behavior under varying load and flux conditions.A series of magnetostatic FEA simulations is performed.To reduce computational complexity,only one motor pole is analyzed by applying anti-periodic boundary conditions along the domain sides and enforcing a zero magnetic vector potential on the external stator boundary.Nonlinear iron material properties are modeled using the appropriate B-H curve.The simulations are carried out by imposing d-and q-axis current components and computing the corresponding flux linkages and electromagnetic torque.Based on these results,both apparent and incremental inductances are extracted and incorporated into the control algorithm.An advanced fictitious flux linkage method combined with a phase-locked loop(PLL)is employed for accurate rotor position estimation.Simulation results confirm that the proposed sensorless control strategy ensures stable operation and high position estimation accuracy over the entire speed range. 展开更多
关键词 Sensorless controller 1 advanced active flux 2 fictitious flux 3 magnetic cross-coupling 4 phase locked loop controller 5
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Low C/N_0 Carrier Tracking Loop Based on Optimal Estimation Algorithm in GPS Software Receivers 认领 引用 被引量：19
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作者 Miao Jianfeng Chen Wu +1 位作者 Sun Yongrong Liu Jianye 《Chinese Journal of Aeronautics》 SCIE EI CAS 2010年第1期109-116,共8页
Suppressing jitter noises in a phase locked loop（ PLL） is of great importance in order to keep precise and continuous track of global positioning system （GPS）signals characterized by low carrier-to-noise ratio（ C... Suppressing jitter noises in a phase locked loop（ PLL） is of great importance in order to keep precise and continuous track of global positioning system （GPS）signals characterized by low carrier-to-noise ratio（ C/No ）. This article proposes and analyzes an improved Kalman-filter-based PLL to process weak carrier signals in GPS software receivers. After reviewing the optimal-bandwidth-based traditional second-order PLL, a Kalman-filter-based estimation algorithm is implemented for the new PLL by decorrelating the model error noises and the measurement noises. Finally,the efficiency of this new Kalman-filter-based PLL is verified by experimental data. Compared to the traditional second-order PLL, this new PLL is in position to make correct estimation of the carrier phase differences and Doppler shifts with less overshoots and noise disturbances and keeps an effective check on the disturbances out of jitter noises in PLL. The results show that during processing normal signals,this improved PLL reduces the standard deviation from 0. 010 69 cycle to 0. 007 63 cycle, and for weak signal processing,the phase jitter range and the Doppler shifts can be controlled within ± 17° and ±5 Hz as against ±25° and ＋ 15 Hz by the traditional PLL. 展开更多
关键词 global positioning system signal processing Kalman filters software radio phase locked loop
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Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector 认领 引用 被引量：4
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作者 陈莹梅 王志功 章丽 《Journal of Semiconductors》 CAS 北大核心 2008年第1期88-92,共5页
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short... A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply. 展开更多
关键词 phase locked loop phase-frequency detector voltage-controlled oscillator jitter locking time
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PLL DEMODULATION TECHNIQUE FOR M-RAY POSITION PHASE SHIFT KEYING 认领 引用 被引量：9
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作者 Qi Chenhao Wu Lenan 《Journal of Electronics(China)》 2009年第3期289-295,共7页
The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation ... The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR. 展开更多
关键词 Phase Locked Loop （PLL） M-ary Position Phase Shift Keying （MPPSK） Phase Detector （PD） Power Spectrum Density （PSD）
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A novel Doppler frequency measurement method based on the closed-loop signal correlation for deep space exploration 认领 引用
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作者 Tao Deng Mao-Li Ma +3 位作者 Qing-Bao He Qing-Hui Liu Ya-Jun Wu Xin Zheng 《Research in Astronomy and Astrophysics》 SCIE CAS CSCD 2021年第9期75-82,共8页
In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modu... In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modules that restricts the tracking performance of phase-locked loop(PLL).Based on the phase relationship between adjacent signals in the time domain,a novel phase detector is presented to replace the arctangent phase detector.The new PLL,which is a closed loop signal correlation algorithm,shows good performance in tracking signals with high precision and the tracking accuracy of frequency of1 second integration is close to Cramer-Rao lower bound(CRLB)when setting proper parameters.Actual data processing results further illustrate the excellent performance of the novel PLL. 展开更多
关键词 Doppler measurement:Cramer-Rao lower bound carrier tracking:phase locked loop signal correlation
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Progress and trends of low-jitter fractional-N PLL 认领 引用 被引量：1
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作者 Jun Yin Haoran Li +2 位作者 Xiaoqi Lin Rui PMartins Pui-In Mak 《Journal of Semiconductors》 EI CAS CSCD 2025年第7期11-14,共4页
Fractional-N phase-locked loops(PLLs)are widely deployed in high-speed communication systems to generate local oscillator(LO)or clock signals with precise frequency.To support sophisticated modulations for increasing ... Fractional-N phase-locked loops(PLLs)are widely deployed in high-speed communication systems to generate local oscillator(LO)or clock signals with precise frequency.To support sophisticated modulations for increasing the data rate,the PLL needs to generate low-jitter output[1]. 展开更多
关键词 PLL sophisticated modulations local oscillator fractional n phase locked loops high speed communication systems clock signals low jitter
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Control of Z-Source Inverter Connected to a Single-Phase AC Utility System 认领 引用
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作者 T. Chandrashekar M. Veerachary 《Journal of Energy and Power Engineering》 CAS 2011年第5期447-454,共8页
This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possi... This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possible because of additional shoot through state introduced in zero state of the conventional inverter pulse width modulation and provides desired output AC voltage. Small distributed generation （DG） system with alternate energy sources requires power conditioning units with low cost, high efficiency and tolerance to wide range of input voltage variation and has to perform various functions such as dc-ac conversion, system control and achieve power quality norms. To meet some of these requirements a two-loop control strategy for ac side control with grid current feedback with PI control and inner filter capacitor current feedback with proportional control and on dc side PID control for Z-source capacitor voltage regulation are employed, which gives good transient response also suppress load and source disturbances effectively. Theoretical analysis of proposed scheme is established and then simulation results are presented to validate proposed control strategy. 展开更多
关键词 Buck-boost Z-source inverter distributed generation phase locked loop.
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Joint frequency offset tracking and PAPR reduction algorithm in OFDM systems 认领 引用 被引量：6
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作者 Lijun Ge Yingxin Zhao +3 位作者 Hong Wu Ning Xu Yu'ang Jin Wenqi Li 《Journal of Systems Engineering and Electronics》 SCIE EI 2010年第4期557-561,共5页
This paper presents an algorithm that aims to reduce the peak-to-average power ratio(PAPR)of orthogonal frequency division multiplexing(OFDM)communication systems while maintaining frequency tracking.The algorithm ach... This paper presents an algorithm that aims to reduce the peak-to-average power ratio(PAPR)of orthogonal frequency division multiplexing(OFDM)communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset(RCFO)using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop(MPLL)is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance. 展开更多
关键词 orthogonal frequency division multiplexing(OFDM) peak-to-average power ration(PAPR) carrier frequency offset complex conjugate multicarrier phase locked loop(MPLL) phase error.
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A 2.4GHz Quadrature Output Frequency Synthesizer 认领 引用 被引量：3
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作者 衣晓峰 方晗 +1 位作者 杨雨佳 洪志良 《Journal of Semiconductors》 CAS 北大核心 2005年第10期1910-1915,共6页
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ... A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm. 展开更多
关键词 frequency synthesizer phase locked loop quadrature VCO phase noise bluetooth
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A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse 认领 引用
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作者 ZHANG Tao ZOU Xuecheng +1 位作者 ZHAO Guangzhou SHEN Xubang 《Wuhan University Journal of Natural Sciences》 CAS 2007年第3期491-495,共5页
A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （... A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time . 展开更多
关键词 low voltage different signal phase locked loop multiplier adaptive charge pump phase noise
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Non-PLL high-precision synchronous sampling method among lots of acoustics acquisition channels for underwater multilinear array seismic exploration system 认领 引用
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作者 JIANG Jiajia CUI Jindong +6 位作者 WANG Xianquan LI Xiaodong ZENG Xianjun ZHOU Dasen YAO Qingwang DUAN Fajie FU Xiao 《Journal of Measurement Science and Instrumentation》 CAS CSCD 2022年第1期41-50,共10页
Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the proble... Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns. 展开更多
关键词 seismic exploration system synchronous sampling non phase locked loop(PLL) local clock asynchronous drive transmission delay
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Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS 认领 引用
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作者 陈莹梅 Chen Xuehui +1 位作者 Yi Lvfan Wen Guanguo 《High Technology Letters》 EI CAS 2014年第2期140-145,共6页
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav... Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply. 展开更多
关键词 Verilog-HDL behavioral level model （ BLM） phase locked loops （ PLL） clock and data recovery （CDR）
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Lock threshold deterioration induced by antenna vibration and signal coupling effects in hypersonic vehicle carrier tracking system of Ka band 认领 引用 被引量：5
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作者 Congying ZHU Lei SHI +2 位作者 Xiaoping LI Yanming LIU Wei AI 《Chinese Journal of Aeronautics》 SCIE EI CAS CSCD 2018年第4期776-781,共6页
The envelope of a hypersonic vehicle is affected by severe fluctuating pressure, which causes the airborne antenna to vibrate slightly. This vibration mixes with the transmitted signals and thus introduces additional ... The envelope of a hypersonic vehicle is affected by severe fluctuating pressure, which causes the airborne antenna to vibrate slightly. This vibration mixes with the transmitted signals and thus introduces additional multiplicative phase noise. Antenna vibration and signal coupling effects as well as their influence on the lock threshold of the hypersonic vehicle carrier tracking system of the Ka band are investigated in this study. A vibration model is initially established to obtain phase noise in consideration of the inherent relationship between vibration displacement and electromagnetic wavelength. An analytical model of the Phase-Locked Loop（PLL）, which is widely used in carrier tracking systems, is established. The coupling effects on carrier tracking performance are investigated and quantitatively analyzed by imposing the multiplicative phase noise on the PLL model. Simulation results show that the phase noise presents a Gaussian distribution and is similar to vibration displacement variation. A large standard deviation in vibration displacement exerts a significant effect on the lock threshold. A critical standard deviation is observed in the PLL of Binary Phase Shift Keying（BPSK） and Quadrature Phase Shift Keying（QPSK） signals. The effect on QPSK signals is more severe than that on BPSK signals. The maximum tolerable standard deviations normalized by the wavelength of the carrier are 0.04 and 0.02 for BPSK and QPSK signals,respectively. With these critical standard deviations, lock thresholds are increased from à12 andà4 d B to 3 and à2 d B, respectively. 展开更多
关键词 Antenna vibration Carrier tracking performance Lock threshold Phase locked loop Tracking Telemetry and Command（TT＆C） signals
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2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit 认领 引用 被引量：5
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作者 刘永旺 王志功 李伟 《Journal of Semiconductors》 CAS 北大核心 2007年第4期537-541,共5页
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de... A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW. 展开更多
关键词 clock recovery data recovery phase locked loop dynamic phase and frequency detector
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