期刊文献+
任意字段
题名或关键词
题名
关键词
摘要
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息
共找到11篇文章
< 1 >
每页显示 20 50 100
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
显示方式：
Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory 认领 引用 被引量：8
1
作者 Xue-Bing Cao Li-Yi Xiao +5 位作者 Ming-Xue Huo Tian-Qi Wang Shan-Shan Liu Chun-Hua Qi An-Long Li Jin-Xiang Wang 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2018年第3期31-41,共11页
Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4... Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields. 展开更多
关键词 3D integration Single event upset (SEU) Multiple cell upset (MCU) Monte Carlo simulation
暂未订购 下载PDF
Application and Development of LTCC for RFIC 认领 引用
2
作者 刘林涛 王进祥 喻明艳 《上海交通大学学报》 EI CAS 北大核心 2007年第S2期123-126,共4页
The trend in the radio frequency IC toward further miniaturization and improved performance drives ongoing technology innovation of new substrate and packaging technologies.In this paper,Hardware technology of RF syst... The trend in the radio frequency IC toward further miniaturization and improved performance drives ongoing technology innovation of new substrate and packaging technologies.In this paper,Hardware technology of RF system was reviewed,and the low temperature cofired ceramics(LTCC) technology was stated to be the best choice.Material development and measurement of Dielectric properties of LTCC technology are introduced.The application of passive embedded component was stated for RFIC design.Design of LTCC library will be the next step for RF system design and simulation. 展开更多
关键词 low temperature cofired ceramics(LTCC) radio frequency IC(RFIC) design library
暂未订购 下载PDF
Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes 认领 引用 被引量：1
3
作者 祝名 肖立伊 田欢 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2010年第5期726-730,共5页
This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended ... This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes. 展开更多
关键词 memory multiple bit upsets improved hamming codes two-dimensional error codes
暂未订购 下载PDF
A Simple Method to Solve the Network Congestion for Spitial Architcture 认领 引用
4
作者 张超 喻明艳 杨兵 《Journal of Shanghai Jiaotong university(Science)》 EI 2017年第1期72-76,共5页
Scheduling algorithm always plays an important role in the spatial architecture for the contradiction between the finite network bandwidth and the abundant execution resources. This article provides a simple method to... Scheduling algorithm always plays an important role in the spatial architecture for the contradiction between the finite network bandwidth and the abundant execution resources. This article provides a simple method to solve the contention for network resource in one of the spatial architecture, i.e. the tera-op, reliable, intelligently adaptive processing system(TRIPS) processor. The method improves the performance of network by increasing the bypass bandwidth which can transmit the data in the internal of every execution unit, and converting the proportion of remote communication by the deep scheduling algorithm. The deeply optimized algorithm is realized to verify the validity of the method, and the performance increase 9% for floating point spec2000 benchmark is got. 展开更多
关键词 scheduling algorithm spatial architecture processor network contention TP 302.7 A
暂未订购 下载PDF
Experimental analysis of an MIM capacitor with a concave shield 认领 引用
5
作者 刘林涛 喻明艳 王进祥 《Journal of Semiconductors》 EI CAS 北大核心 2009年第10期55-58,共4页
A novel shielding scheme is developed by inserting a concave shield between a metal–insulator–metal （MIM）capacitor and the silicon substrate.Chip measurements reveal that the concave shield improves the quality fa... A novel shielding scheme is developed by inserting a concave shield between a metal–insulator–metal （MIM）capacitor and the silicon substrate.Chip measurements reveal that the concave shield improves the quality factor by 11%at 11.8 GHz and 14%at 18.8 GHz compared with an unshielded MIM capacitor.It also alleviates the effect on shunt capacitance between the bottom plate of the MIM capacitor and the shield layer.Moreover,because the concave shields simplify substrate modeling,a simple circuit model of the MIM capacitor with concave shield is presented for radio frequency applications. 展开更多
关键词 MIM capacitor concave shield quality factor model
暂未订购 下载PDF
Design procedure for optimizing CMOS low noise operational amplifiers 认领 引用
6
作者 李志远 叶以正 马建国 《Journal of Semiconductors》 EI CAS 北大核心 2009年第4期90-94,共5页
This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noi... This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE. 展开更多
关键词 design procedure noise operational amplifier optimize
暂未订购 下载PDF
Process variation robust current-mode on-chip interconnect signaling scheme 认领 引用
7
作者 王新胜 胡诣哲 喻明艳 《Journal of Semiconductors》 EI CAS CSCD 2014年第2期120-125,共6页
We propose a novel bias circuit, which can help a promising current-mode signaling （CMS） scheme （CMS-bias） enhance the robustness against process variation but consume less energy than the original bias circuit in... We propose a novel bias circuit, which can help a promising current-mode signaling （CMS） scheme （CMS-bias） enhance the robustness against process variation but consume less energy than the original bias circuit in this scheme. Monte Carlo and process corner analysis are carried out using HSPICE in the Global Foundry 0.18 μm process. Monte Carlo analysis shows that the CMS-bias with proposed bias circuit （CMS-proposed） and the CMS-bias with original circuit （CMS-original） have the same robustness against the variation, but the former offer a 9% reduction in power consumption. The process corner analysis shows that the average power and delay of the CMS-proposed don＇t change much in different process corners, especially in FS and SF corner. In addition, parameter sensitivity analysis shows that the process variation in long wires has little influence on the delay of the CMS scheme, but the variation in the effective length of MOSFETs influences the performance of the CMS scheme very much. 展开更多
关键词 global interconnect current-mode Monte Carlo
暂未订购 下载PDF
A New Synchronization Algorithm for VHDL—AMS Simulation 认领 引用
8
作者 肖立伊 叶以正 李滨 《Journal of Computer Science & Technology》 SCIE EI 2002年第1期28-37,共10页
VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorith... VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation. 展开更多
暂未订购 下载PDF
A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation 认领 引用 被引量：4
9
作者 周前能 王永生 来逢昌 《Journal of Semiconductors》 EI CAS 北大核心 2009年第4期95-100,共6页
A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, wh... A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA. 展开更多
关键词 low-dropout regulator AC-boosting and active-feedback frequency compensation capacitor-flee
暂未订购 下载PDF
Current mode ADC design in a 0.5-μm CMOS process 认领 引用 被引量：2
10
作者 孙泳 来逢昌 叶以正 《Journal of Semiconductors》 EI CAS 北大核心 2009年第6期88-93,共6页
This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerousl... This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and portability.Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue IP.Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA.Adopting the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,respectively.The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique. 展开更多
关键词 current mode analog to digital converter pipelined
暂未订购 下载PDF
A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs 认领 引用 被引量：1
11
作者 张建伟 叶以正 +1 位作者 刘滨达 兰金宝 《Journal of Semiconductors》 EI CAS 北大核心 2009年第6期126-131,共6页
A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high searc... A novel cascaded charge-sharing technique is presented in content-addressable memories（CAMs）,which not only effectively reduces the match-line（ML） power by using a pre-select circuit,but also realizes a high search speed.Pre-layout simulation results show a 75.9% energy-delay-product（EDP） reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method.Based on this technique,a test-chip of 64-word × 144-bit ternary CAM（TCAM） is implemented using a 0.18-μm 1.8-V CMOS process,achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs. 展开更多
关键词 content-addressable memory energy-delay-product cascaded charge-sharing
暂未订购 下载PDF
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
上一页 1 下一页 到第 页
在线咨询 使用帮助 返回顶部 意见反馈